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Part Number: ADC31JB68 Tool/software: Hi sir,
I am currently working with the ADC31JB68RTAT IC and have encountered an issue while using the IBIS model for SI simulation. According to the datasheet, pins 23 to 26 of the IC are output pins. However, in…
Hi David,
I'm filling out the Excel sheet for this. I am having difficulty completing the ADC tab (I'm also referencing your slap161 document):
Fs [GSPS]: is this the sampling rate of the ADC alone?
- Decimation: is this the case for an ADC with…
Part Number: ADC31JB68 Tool/software: I'm planning to use an ADC31JB68 in a design - I usually look to the associated EVM to finalize the ciruitry I need to develop around it. I see the ADC31JB68EVM exists, but only a user's manual is available without…
Hi Rob,
we got it working. It was the clock generation chip, which provided the main clocks for the ADC and the FPGA.
We use a LMK04821. We read out the regitsters for the lock bits, they were sets, but the clock signal had a huge jitter.
We found two…
Part Number: ADC31JB68 Other Parts Discussed in Thread: LMH5401 , LMH6553 , TINA-TI Hi, I will use the ADC31JB68 device in my design and I am looking for a drive to it for unbalancing to balancing convertion.
The input signal goes from DC to 200MHz.
Do…
Part Number: ADC31JB68 Hi, since the ADC31JB68B has a small input range (1.7Vpp) I did not find any kind of TVS or zener that I could use to protect it against over voltage.
I would like to know if you have any suggestion?
Thank you,
Rodrigo
Part Number: ADC31JB68 Hi, the ADC31JB68 datasheet shows the baluns in the "current configuration mode" to convert the unbalanced to balanced signal in the analog input.
Is there any special requirement to use this structure of the baluns for…
Part Number: ADC31JB68 Hi Team,
We have received this inquiry from our customer,
I have an analog signal with wider dynamic range than the ADC can handle, so the signal could regularly exceed the ADC's analog input range. These excursions will typically…
Part Number: ADC31JB68 Hello, I will have only one ADC31JB68 connected in a FPGA (JESD204) in my design. As there is no multiple devices does I need to use the SysRef signal input of the ADC? If no, can I tie the SysRef input to zero?
Thank you,
Rod…
