Part Number: ADC32J44 My customer has asked the following:
We noticed in the datasheet that K is configurable through SPI. We would like to know what the range of this configuration parameter is. Can we set it to 0 and have only 1 frame per LMFC.
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Part Number: ADC32J44 Do we need to meet setup/hold time of the SYNC~ signal when working in subclass 0? Reason is we have HW components that might make this not possible.
If that is required, can we drop the SYNC~ signal and use soft synch instead…
Other Parts Discussed in Thread: ADC32J44 , ADC34J44 Hello.
I'm a bit confused about the adc32j44 datasheet ( http://www.ti.com/lit/ds/symlink/adc32j44.pdf )
The datasheet states "The detailed frame assembly for quad-channel mode is shown in Figure…
Part Number: ADC32J44 Hello.
I am not using the SYNC pins (42 and 43) in my application, as I am using the SYSREF+/- inputs instead.
If the SYNC pins are not used, should I float the pins, or tie SYNC+ to DVDD and SYNC- to GND?
Thanks for the help…
Part Number: ADC32J44 Hi,
I'm setting Register 0Ah. When I set as 1001, it should be 0,2399, 8192, 13984, 16383, 13984, 8192, and 2399, but I get 0 3915 5537 3915 0 12468 10846 12468 . I want to know how to find the root cause.
Other pattern in Register…
Part Number: ADC32J44 Hi,
I was wondering if you have a reference design for evaluating the ADC32J44 with the ZCU102 zynq ultrascale+ evaluation board and the TI HSDC pro software. If not could you point me to the FPGA HDL design files for the ZC706…
Part Number: ADC34J44 Other Parts Discussed in Thread: ADC32J44 If the PDN is pulled up from power up, is it possible to acess the device through the SPI interface, without first driving the PDN pin low?
Whilst in power down what do the device outputs…
