Part Number: ADC32RF80 Hello
I would like to configure the ADC32RF80 for decimate by 16. I have been successfully using the ADC32RF80 for decimate by 4 and 8 in the following configuration:
Decimate by 4:
LMFS = 8422
PLL MODE = 20X
JESD MODE…
Part Number: ADC32RF80 Good day Colleagues,
Could you tell me, what is an input impedance of the ADC32RF80? A picture in the datasheet shows 50Ohm, but in a table it's 60 Ohm DC.
Do we have S parameters for simulation?
Thank you, Mikhail
Part Number: ADC32RF80 Hi
If I set the same SYSREF and CLK signals for two ADC32RF80 and set one input signal to their RF inputs, can I get similar synchronous signals from ADC's outputs? Or their NCO phases wil not be the same and so phases of output…
Part Number: ADC32RF80 Hi
In the datasheet for ADC32RF80 all calculations and graphs was made for Fs = 2949.12M. But description on your site say Fs_max = 3000M, so Fs can be 3000M. On the other hand, the built-in NCO has resolution 16 bits, (2^16 …
Part Number: ADC32RF80 Other Parts Discussed in Thread: LMK04828 , Hello! I have custom board with two ADC32RF80 + LMK04828 + FPGA. I run ADC on Fs = 2400 Mhz, Single-Band Complex Output, Decimation = 32, LMFS = 2441. Both ADCs and FPGA clocked from one…
Part Number: ADC32RF80 Hi all,
We know the ADC32RF80 is a 14bit IC,but the fpga has trunccated the14bit data that received from the ADC output to 12bit for power calibraion.We see there is a large dc in the center of the spetrum when FFT analyse the…
Part Number: ADC32RF80 DEARS.
Customer is ADC32RF80 is designed and used.
Fs = 2949.12Mhz
Interleaving spur occurs at 2580.48MHz.
The frequency band you are using.
In this case, is it appropriate to use the command "Steps for freezing the corrector…
Part Number: TSW40RF80EVM Other Parts Discussed in Thread: ADC32RF45
Connect the analog board TSW40RF80 to the FPGA board TSW14J57. The FPGA board has a JESD IP that receives the ADC32RF45 analog board.
It synchronizes only when the config data is…
I presume that you are driving both ADC inputs and that each input is phase matches. The programming of the NCO can introduce a phase variation. You can synchronize the NCO with a software sync that will synchronize to the SysRef. The 'J56 card will capture…
I'm not familiar with AIF2 interface and based on https://www.ti.com/lit/ug/sprugv7e/sprugv7e.pdf , you can't directly connect to JESD204B interface. Please check with processor team for any suggestion they may have.
