Part Number: ADC32RF80 hi
i have ADC32RF80EVM and TSW14J56. and use lmx2582internal clock and bypass mode. The signal source is 160Mhz, 1.3VVpp. But you can't get the right data. Some data is always 0.
Attachments are screenshot files, which are 12…
Part Number: ADC32RF80
hi team：
We have a block ADC32RF80EVM development board for use with the TSW14J56EVM. There are a few questions:
1. ADC32RF80 is 14 bits, the peak-to-peak value is 1.3V, and the full-scale count is 16384. But to use DDC, I set…
Part Number: ADC32RF80 DEARS.
Customer is ADC32RF80 is designed and used.
Fs = 2949.12Mhz
Interleaving spur occurs at 2580.48MHz.
The frequency band you are using.
In this case, is it appropriate to use the command "Steps for freezing the corrector block…
Hello Renan,
The ADC32RF80 and DAC38RF80 on the TSW40RF80 cannot support flexible, programmable FIR DDC, DUC filtering, resectively. The FIR on the ADC32RF80 and DAC38RF80 are fixed and hardcoded. The customer will have to design their own RTL code on…
Part Number: ADC32RF80 Other Parts Discussed in Thread: TSW40RF80EVM , Hi
I used TSW40RF80EVM with ADC32RF80 for the digitization of the pulses filled with sinuses 1005 M. Then ADC DDC mixed them with 1000M, decimated by 4 and filtered. TSW40rf80evm is…
Part Number: ADC32RF80 We have a question about Offset corrector block in adc32rf80. Harmonics of which level we should expect at frequencies which is multiple of 1/8 of sample rate in case of this block is disabled (not freezed) with "DIS OFFSET CORR…
Part Number: ADC32RF80 Other Parts Discussed in Thread: ADC32RF45EVM , LMX2582 , ADC32RF45 Tool/software: Code Composer Studio Hi TI
We want to develop ADC32RF80, but there are too many registers.
Is there any reference code that can help us?
Can it be…
Part Number: ADC32RF80 Dears.
We are using Nyquist zone (0 ~ Fs / 2) for 3G sampling.
In this case, there is a phenomenon that the signal is rejected when inputting 750MHz CW.
We will ask you to confirm whether there is an input restriction for Fs / 4…
Part Number: ADC32RF80 Good day,
I have a design on an FPGA that includes two JEDS204B data receivers. The first receives data from channel A of the ADC32RF80 while the second receives data from channel B. When I configure the DDCs of channel A to Divide…
Part Number: ADC32RF80 Dears.
The customer board was designed in ADC32RF80. The setting values are as follows.
L: 4 M : 4 F : 2 C : 1 K : 32 Scramble : Off Sampling : 3Ghz Serdesclk : 250M Jesdcore clk : 125M sysref : 7.8125M
The data output from the ADC32RF80…
