Part Number: ADC3421 Tool/software: I would like to better understand the various power-down modes of operation for the ADC3421. Register 15h has bits assigned for powering down individual channels (A, B, C, D). There is also a STANDBY bit and a Global…
Part Number: ADC3421 Hello,
We are designing with the ADC3421.
What is the recommended termination methods for unused ADC inputs, unused LVDS outputs, unused SYSREFM, SYSREFP?
Thank you, Keith
Part Number: ADC3421-Q1 Hi Experts, Good day. I need your help with the frequency information for SYSREF pins.
What should be the required frequency?
Keep safe. Regards, Josel
Part Number: ADC3421 Hello,
according to page 43 of the datasheet, the clock can be driven by a single-ended CMOS clock. What signaling levels are best used for this purpose? 1.8V/2.5V/3.3 V LVCMOS/LVTTL?
(SNR degradation due to increased jitter is not…
Part Number: ADC3421 Other Parts Discussed in Thread: OPA4991 Hi,
What is the maximum capacitance I can put on the VCM pin. I am using VCM to bias my ac coupled inputs and I am getting some crosstalk and noise coupling between channels - I believe via…
Part Number: ADC3421 Hi,
I am working on interfacing the ADC3421 to my FPGA using single serial link (1 per output). The ADC is running at 25MSPS and I have had some trouble getting the correct output out of all the different test patterns. I am finding…
Hi Dan,
I created a timing diagram (using "wavedom" - very helpful tool) to visualize the timing in 2-wire mode, please see below.
Regarding your explanation above on the increasing amplitude of the internal clock - if it is as you descibe…
