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  • ADC342x standby power down

    Other Parts Discussed in Thread: ADC3423 Hello, In the register 15h, Bit 3, it is written "The ADCs of both channels enter standby": Which pair of both channels AB or CD enter to the standby mode ? During the standby power down, is the device…

  • ADC3424 EVB

    Other Parts Discussed in Thread: ADC3424 , ADC3423 Hello, Does the evaluation board of the ADC3424 support a clock of 80 MHz instead of 125 MHz ?
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  • RE: Recommended clock distribution device

    Resolved
    Hi I made a typo on the previous message, I'm using ADC3423 (not the JESD204B) The config for DAC38J84 is LMF=244 The DACCLK for DAC38J84 is 1920MHz, DACCLKC for DAC3482 is 960MHz The data rate from FPGA is 240MSPS to both devices. DATACLK to…

  • ADC342x application note

    Other Parts Discussed in Thread: THS4541 Hello I would like to know if there is an application note about the interfacing driving input circuit when a zero IF signal is received. If not, what is the recommended circuit ? Thanks for your support. Lau…

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