Part Number: ADC3443 Hi
we have some quenstions about ADC3443.
first one , how to connect sysref pin to the FPGA pins ,the FPGA dataoutput pins are LVDS 2.5V level.As the figure below shows the connection status.
the second questions is about…
Part Number: ADC3443
Hi Team,
Posting on behalf of our customer.
I have a question about how to achieve synchronization among multiple ADC3443 devices. There are four devices on the board. In the datasheet of ADC3443, the sysref pin can be used…
Part Number: TSW1418EVM Other Parts Discussed in Thread: ADS4242 , ADC3443 , , TSWDC155EVM Tool/software: Hello,
Is the TSW1418EVM compatible with the ADC3443 or ADS4242 EVMs? If not, what is the best path forward to evaluate the ADC3443 or ADS4242…
Part Number: ADC3443
I’m fairly advanced in designing in the ADC3443 and now looking at the detail on the design.
I came across this PCN (on the Digikey site)
https://media.digikey.com/pdf/PCNs/Texas%20Instruments/PCN20161114000.pdf
Is this…
Part Number: ADC3443 SYSREFM LVDS inputs needs an external termination? I’m 90% sure that it doesn’t as there is no mention of termination in the D/Sheet or in the reference design. I was just wondering if you can confirm that the 100R LVDS termination…
Part Number: ADC3443 Hi,
We will use the FPGA's LVDS driver to drive SYSREF.
The output characteristics of this driver are 1.25V common mode voltage and 0.25 ~ 0.6V differential swing.
I realized in past thread that this circuit requires an external…
Part Number: ADC3443 Hello
I would like to know if and how I can set an input voltage different from 2Vptp ?
It is written in the datasheet (page 6) for frequencies < 600 MHz: 1Vptp. Do you stay with 14 bits at 1 Vptp ?
How does the GUI take into…
Part Number: ADC3443 Hello,
I would like to know how to perform multi chip ADCs synchronization when I'm using only LVDS wires and not JESD204B, and when I'm not using the internal ADC clock divider ?
Thanks for your support
Lolo
Part Number: ADC3443 Other Parts Discussed in Thread: THS4541 Hi,
I have a pseudo-differential output from a sensor that has to be conditioned to match the input of the ADC with optimal noise performance.
The signal has the following shape :
…