Part Number: ADC34J44 Hi Team
Can you help to review the the below circuit used for ADC34J44 input Impedance matching? Customer refer to our EVM's design.
Part Number: ADC34J44 Hi, Team:
When the input signal is greater than 0dbfs, the signal collected by FPGA becomes more spurious, like overflow.
I want to ask what is the maximum input signal allowed by adc34J44.
Part Number: ADC34J44 https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/747093/adc34j44-jesd204b-configuration-check?tisearch=e2e-sitesearch
Hi Team
What is the meaning of 'N' in this link post? the Divide?…
Part Number: ADC34J44 Hi team
As mentioned in Datasheet, Digital output level is CML, if the receiver is just supported LVDC ,if customer can change by impendence matching? How?
Thanks!
Part Number: ADC34J44 Other Parts Discussed in Thread: ADC32J44 If the PDN is pulled up from power up, is it possible to acess the device through the SPI interface, without first driving the PDN pin low?
Whilst in power down what do the device outputs…
Part Number: ADC34J44 Hi,
We are planning to use this JESD interface daughter board with our FPGA.
I want to know the FMC connector pinouts.
Please send me the schematic asap.
Regards,
Harika.
Part Number: ADC34J44 I am wondering if the output code rolls over when there is an over-range event? Or is it held at the max value? I see that the data is rolling over. I cannot tell from the datasheet what is the expected behavior.
Thank you.
Best…
Part Number: ADC34J44EVM Other Parts Discussed in Thread: ADC34J44 , AM3357 Hi,
I bought ADC34J44EVM and tried with ADC3000 GIU application configure chip ADC34J44. I added ti SPI pinheader logic analyser. I tried write register 0x02 to 0x02 and register…
Part Number: ADC34J44 Hi,
I read in another post that LVDS signalling works to drive the SYNC input. But the common mode specified in the datasheet is 0.9V. What do I do if the common mode of the LVDS driver (e.g. FPGA) is 1.25V?
Thank you.
Best regards…
Part Number: ADC34J44 Hi,
I intend to operate this part in Subclass 2. But I have multi tx and rx environment and I need deterministic latency across all those tx and rx jesd204b pairs. I have 5 of ADC34J44 paired with 5 corresponding JESD204B RX in 5…