Part Number: ADC3643 Tool/software: I'm looking into the ADC3643 datasheet and have a couple of questions about the timing that provided in this file. First of all tcd (as an example -0.7 ns) is shown as a negative number and I don't understand dos my…
Part Number: ADC3643EVM Other Parts Discussed in Thread: ADC3644 , ADC3642 Tool/software: Hi
We are working with ADC3643EVM revision E. We couldn't find related design files and layout files for this revision. Please share the related document with…
Part Number: ADC3643 Other Parts Discussed in Thread: ADC3644EVM , ADC3664EVM , THS4541 , ADC3669 , TSWDC155EVM Tool/software: I'm looking for an ADC EVK and Capture Card pairing, I've looked at a lot of offerings but have failed to come up with anything…
Part Number: ADC3643 Dear Technical Support Team,
I have six questions for ADC3643.
Q1 In 8.5 on page 43 of the data sheet, it is stated that it can be operated in the default mode without being controlled by SPI. What is the default interface mode…
Part Number: ADC3643 Other Parts Discussed in Thread: ADC3683 Hello,
I am planning to use the ADC3643 chip (also maybe ADC3683 later) in the following configuration: 64MHz sample clock, decimate by 32, 20 bit 2 wire DDR output. As far as I can calculate…
Part Number: ADC3643 The Clock Input spec's a typical input common mode voltage of 0.9, but not a min or max. What range can the common mode voltage be for the CLK input? For example, can I DC couple the CLK signal from an LVDS signal that has >250mV…
Part Number: ADC3643
Hi Team, In reference to the original question, can we also request for the file with the register writes to configurate the ADC3643 in DDR / 14bit / 65MSPS? Thanks in advance! Kind Regards, Jejomar
Part Number: ADC3643 Other Parts Discussed in Thread: ADC3641 , ADC3683 Hello,
We plan to use ADC3641 in our new project. I download the EVM design files and found it use FPGA to get ADC results,
1, Why use FPGA?
2, Can we use MCU to get it? If…
