Hi Tom,
Making sure I am understanding your issue correctly: you are using the ADC3660 in Real Decimation by 16 mode (you have determined that in this mode the Sample CLK and DCLK are the same frequency). You have first tested with Sample CLK and DCLK…
Hi Matteo,
Oh yes, you are correct - my mistake. Thanks for reading up. NSD value should remain constant regardless of the decimation factor. If you divide the fs /16 in the excel calculator, then you will see the expected NSD is ~152 dBFS/Hz. I setup…
Hi Kelsey,
Yes you are correct, the ADC GUI does not print out the register writes for the CDCE6214 chip. CDC clock enable just enables / disables the onboard clock. If using external clocking, it is best practice to have it toggled off.
You can download…
Hi Ryan,
I set up the ADC3660EVM in the lab and configured it as you describe. I measured the FCLK duty cycle to be 50%. Can you read registers 0x20, 0x21, 0x22? These are the registers responsible for setting the FCLK duty cycle.
Regards, Amy
Other Parts Discussed in Thread: ADC3662EVM Hi,
Good Day. Customer is need some help picking out an ADC Eval Board.
He would ideally like a stand alone eval board with a GUI/app to go along with it. At least 14 bits of resolution and at least 10Msps of…
Hello,
The ADC3660EVM GUI can be used to program the ADC3683EVM registers via the FTDI chip. The below link will download the GUI.
https://www.ti.com/lit/zip/SBAC271
Please utilize the ADC3683EVM User's Guide for getting started. See link below.
…
Hi Vandenplas,
Yes, the ADC3660 can sample from 0.5 MSPS to 65 MSPS, and can accept analog input signals from DC to hundreds of MHz. For an example, please see the ADC3660EVM schematic where we use an amplifier (THS4541) to DC couple the analog input…
Hi Pieter,
Yes, there will be a short transition/discontinuity in the NCO output as it changes to its new frequency. If holding the SYNC pin (or register) in a "high" state, the NCO will not be present. The main idea is to provide a pulse to quickly update…
Hi,
Can you share a picture of the noise you are seeing? What are the registers you are writing in order to configure the ADC in 1 wire decimation mode?
Here is an FFT of the complex data with a 10 MHz NCO applied (no analog input present).
Here is an…
