Part Number: ADC3662 Dear TI.
We are testing a board with the ADC3662 on it configured to use the internal DDC.
The system works with a fixed sampling frequency, but the carrier frequency can be different.
When the low frequency carrier is used, the resulting…
Part Number: ADC3662 Other Parts Discussed in Thread: THS4541 In adc3662`s datasheet, chapter 6.6 say that input full scale is 3.2 Vpp and input commom model voltage is 0.95V. So the input range is from (0.95-1.6)V to (0.95+1.6)V. Is it right? However…
Part Number: ADC3662 Dear all,
We are designing a board with the ADC3662 configured to use the internal DDC feature with complex decimation.
We are wondering what will happen in case of an overflow?
We do not see any dedicated pin or status bit to get this…
Part Number: ADC3662 Dear all,
We are designing a board with the ADC3662 configured to use the internal DDC feature with complex decimation.
To simplify the design, we are considering to generate the DCLKIN clock with the FPGA internal PLL.
This clock is…
Part Number: ADC3662 Hi,
Good Day.
We need to know the Differential Signal Level for CLKP and CLKM.
Datasheet doesn't mention what is common mode required on the differential clock input.
We need to know the levels of all the differential signals…
Part Number: ADC3662 Other Parts Discussed in Thread: , ADC3661 Dear All
we plan to use ADC366x 16 bit dual channel ADC for prototyping. From data sheet it is not understood how we can use ADC without any digital filtering (DDC)/decimation.
Our interpretation…
Part Number: ADC3662 In 8.5.2, it says the interface can function with SCLK <=12MHz.
But in the table below it shows it can go to 20MHz:
Which is correct?
Part Number: ADC3662 Dear All!
Chapter 6.8 (page 13) of ADC3662 data sheet (SBAS991A) defines timing requirement for t CD (DCLK rising edge to output data delay) and t DV (data valid).
For our implementation we assume t CD is valid also for falling edge of…
Part Number: ADC3662
Hi Experts,
Good day. Seeking your advise on this query from Cx:
"ADC3662 digital output is not correct. Even when a test pattern of all ones is loaded up, DA0 and DB0 are low for the first bit after the frame clock transition.…