Part Number: ADC3662 Tool/software: Hi,
the datasheet says that the REFBUF pin should be have a delay to the AVDD by 2ms:
In the ADC3662EVM schematic is the REFBUF pin connected to AVDD directly via a jumper:
So in my opinion there is no delay…
Part Number: ADC3662 Other Parts Discussed in Thread: , THS4541 Tool/software: Hi,
I'm using the ADC3662 with the THS4541 as FDA like at ADC3662EVM.
In the datasheet of the ADC3662 it's mentioned that protection diodes may be needed to protect the…
Part Number: ADC3662 Other Parts Discussed in Thread: , ADC3661 Dear All
we plan to use ADC366x 16 bit dual channel ADC for prototyping. From data sheet it is not understood how we can use ADC without any digital filtering (DDC)/decimation.
Our interpretation…
Part Number: ADC3662 Dear all,
We are designing a board with the ADC3662 configured to use the internal DDC feature with complex decimation.
We are wondering what will happen in case of an overflow?
We do not see any dedicated pin or status bit…
Part Number: ADC3662 Dear all,
We are designing a board with the ADC3662 configured to use the internal DDC feature with complex decimation.
To simplify the design, we are considering to generate the DCLKIN clock with the FPGA internal PLL.
This…
Part Number: ADC3662 Dear TI.
We are testing a board with the ADC3662 on it configured to use the internal DDC.
The system works with a fixed sampling frequency, but the carrier frequency can be different.
When the low frequency carrier is used…
Part Number: ADC3662 In 8.5.2, it says the interface can function with SCLK <=12MHz.
But in the table below it shows it can go to 20MHz:
Which is correct?
Part Number: ADC3662
Hi Experts,
Good day. Seeking your advise on this query from Cx:
"ADC3662 digital output is not correct. Even when a test pattern of all ones is loaded up, DA0 and DB0 are low for the first bit after the frame clock transition…
Part Number: ADC3662 Hi,
Good Day.
We need to know the Differential Signal Level for CLKP and CLKM.
Datasheet doesn't mention what is common mode required on the differential clock input.
We need to know the levels of all the differential signals…