Part Number: ADC3663 We are trying to enable the test pattern output on both channels with 16 bit output resolution. A custom pattern 0xaa and 0xbb is written in registers 0x14 and 0x15 and to enable test pattern 0x6C is written to the register 0x16.The…
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i has ADC3663 EVM +LVDS FPGA Interposer Card,without TSW1400EVM. Can I export the register configuration value by "ADC35XX EVM GUI'? I can't find " 'save config file" button in "ADC35XX EVM GUI".
Part Number: ADC3663 Other Parts Discussed in Thread: ADS5263 , Hi Team,
The customer would like to use ADS5263 but power consumption doesn't meet their spec.
Is it possible that ADC3663 be used the same as ADS5263 by bypassing the DDC?
Part Number: ADC3663 hi,
According to table 8-22,need to set in Ramp Pattern mode for 16-bit ADC.how to set REG0X14/15/16?
1. REG0x15[bit7-5]=010), chose Ramp Pattern mode;
2.to set Ramp pattern for 16-bit ADC), " 00100" should be sent to reg0x14…
Part Number: ADC3663 hi,
There are some questions about clock signals for sample clock , Dclkin and Fclk for ADC3663. pls kindly help check them.
1. Be sample clock for (CLKP/CLKN) and Dclkin must generated from a same clock generator? if no, what…
Part Number: ADC3663 I have 2 differential amplifiers giving same output signal. To rout analog inputs without vias i need to connect the input channels as in image. The differential input varies from 1.2 to -1.2V.
Is below one the effect of this connection…
Part Number: ADC3663 Hi Expert,
Would like to clarify:
At 3.2 Vpp differential for full scale the max positive swing can only be 1.6 Vpp differential. So the device is going to clip when AINP is 0.8 volts above Vcm and when AINM is 0.8 volts below Vcm…
Part Number: ADC3663 Hello, I am using ADC3663 and the settings are as follows when sampling at 50MHz: 2wire, 16bits, and DDC set to bypass, CLK input clock is 50MHz, and DCLK input clock is 200MHz. However, the FCLK clock output by AD is not 25MHz and…
Part Number: ADC3663 Hello,
I have two questions that contribute to the same phenomenon.
1.The manual states that turning on DLL PDN when Fs is less than 40M can improve the SNR, but when I turn it on, the baseline of data collection will change every…
Part Number: ADC3663 Other Parts Discussed in Thread: DS25BR101 , DS25BR150 Hi Team, ADC3663 is Serial LVDS(VOD=700mVpp, VCM=1.0V) output. Post device is LVDS(VOD=350mVpp, VCM=1.2V) input.
Is it possible to receive the signal of Serial LVDS at LVDS? Is there…