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  • RE: ADC3663: register Configuration for ADC3663

    Resolved
    Chase i has ADC3663 EVM +LVDS FPGA Interposer Card,without TSW1400EVM. Can I export the register configuration value by "ADC35XX EVM GUI'? I can't find " 'save config file" button in "ADC35XX EVM GUI".

  • ADC3663: test pattern register

    TI Thinks Resolved
    Part Number: ADC3663 hi, According to table 8-22,need to set in Ramp Pattern mode for 16-bit ADC.how to set REG0X14/15/16? 1. REG0x15[bit7-5]=010), chose Ramp Pattern mode; 2.to set Ramp pattern for 16-bit ADC), " 00100" should be sent to reg0x14…
    • Answered

  • ADC3663: clock inputs for sample Clock(CLK) , Dclkin

    Resolved
    Part Number: ADC3663 hi, There are some questions about clock signals for sample clock , Dclkin and Fclk for ADC3663. pls kindly help check them. 1. Be sample clock for (CLKP/CLKN) and Dclkin must generated from a same clock generator? if no, what…
    • Resolved

  • ADC3663: About ADC3663 DDC bypass mode

    TI Thinks Resolved
    Part Number: ADC3663 Other Parts Discussed in Thread: ADS5263 , Hi Team, The customer would like to use ADS5263 but power consumption doesn't meet their spec. Is it possible that ADC3663 be used the same as ADS5263 by bypassing the DDC?
    • Answered

  • ADC3663: Effect of swapping P and N at inputs of ADC

    Resolved
    Part Number: ADC3663 I have 2 differential amplifiers giving same output signal. To rout analog inputs without vias i need to connect the input channels as in image. The differential input varies from 1.2 to -1.2V. Is below one the effect of this connection…
    • Resolved
    • Answered

  • ADC3663: FS input voltage

    Resolved
    Part Number: ADC3663 Hi Expert, Would like to clarify: At 3.2 Vpp differential for full scale the max positive swing can only be 1.6 Vpp differential. So the device is going to clip when AINP is 0.8 volts above Vcm and when AINM is 0.8 volts below Vcm…
    • Resolved

  • ADC3663: The baseline changes after DLL PDN is turned on or when MCLK is switched

    Part Number: ADC3663 Hello, I have two questions that contribute to the same phenomenon. 1.The manual states that turning on DLL PDN when Fs is less than 40M can improve the SNR, but when I turn it on, the baseline of data collection will change every…
    • Answered

  • ADC3663: FCLK error in DDC bypass

    Resolved
    Part Number: ADC3663 Hello, I am using ADC3663 and the settings are as follows when sampling at 50MHz: 2wire, 16bits, and DDC set to bypass, CLK input clock is 50MHz, and DCLK input clock is 200MHz. However, the FCLK clock output by AD is not 25MHz and…
    • Resolved

  • RE: ADC3663: ADC output problem after power down and then up

    Hi John, Yes we have hardware in our lab which can be used to verify this. Can you zip up your SPI sequence and upload here so someone in our lab can take a look using 50MSPS sample rate? Also, I am specifically interested in seeing the data for when…
    • Answered

  • ADC3663: SLVDS and LVDS

    Resolved
    Part Number: ADC3663 Other Parts Discussed in Thread: DS25BR101 , DS25BR150 Hi Team, ADC3663 is Serial LVDS(VOD=700mVpp, VCM=1.0V) output. Post device is LVDS(VOD=350mVpp, VCM=1.2V) input. Is it possible to receive the signal of Serial LVDS at LVDS? Is there…
    • Resolved

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