Part Number: ADC3664 Tool/software: Hi support team,
I select ADC3664 as ADC for my design with sample rate is 80MSPS. The input signal like the attached image. it likes a pulse with frequency 40MHz. (maximum). I read in the datasheet and it mentions…
Part Number: ADC3664 Tool/software: Dear Technical Support Team,
I'd like to use six ADC3664 on the same board and it has four clks.
Do you have any idea to reduce or sharing clocks?
CLK (in )
DCLKIN(in)
DCLK(out)
FCLK(out)
According to previous…
Part Number: ADC3664 Tool/software: I have a situation where 4 of the ADC3664 devices will be used in a design. The devices will operate from the same input clock source and are intended to be synchronous.
My question is: can the FPGA receiving the the…
Part Number: ADC3664 Hi,
I have a question about table 9-3, 9-4 and 9-5 of the datasheet of ADC3664.
In each table, frequency of data is twice the dclk frequency but regarding timing diagram and because we are in DDR mode, my guess is that the frequency…
Hi Bernhard,
Sorry for the delay. See the links below to help describe this.
https://www.analog.com/media/en/training-seminars/tutorials/MT-024.pdf
https://www.analog.com/media/en/training-seminars/design-handbooks/Data-Conversion-Handbook/Chapter5.p…
Part Number: ADC3644 Other Parts Discussed in Thread: ADC3664 , Dear Technical Support Team,
Do you have Comparison chart(pdf or ppt) for ADC3644(DDR CMOS or Serial CMOS) vs ADC3664(Serial LVDS).
I thought it was just the difference between DDR CMOS or Serial…
Part Number: ADC3664 Hi, In my project, I am using 3 ADC3664. I have a doubt regarding the usage of PDN/SYNC pin. Here I am implement a design as per the data got from Datasheet. Can you please check it with for synchronization of all 3 ADCs. Thanks
Part Number: ADC3664 Hi Team,
Please help answer the following questions.
1) is the SNR calculated by analyzing FFT data after the A/D conversion?
2) the signal input to A/D is the signal from the measuring instrument( e.g. Signal Analyzer or Signal Generator…
Part Number: ADC3664 Hi Team,
We're selecting one 100MSPS ADC, the preferred part is AD3664. but in d/s, it is said this ADC architecture is SAR NOT pipeline, may I know why SAR ADC can support such high sample rate? my concern is that if this has crosstalk…
