Part Number: ADC3664 Hello,
I have a question regarding the clock requirements for the ADC3664: Does the sampling clock (CLKP/M) and the DCLKIN (DCLKINP/M) need to be frequency-locked to the same source?
I could not find a clear statement in the…
Part Number: ADC3664-SP Hello,
We would like to use a Radiation-hardness-assured (RHA) QMLV ADC3664-SP. Do you have a dual hardened PLL for in-phase frequencies that you could supply to the ADC?
regards
Part Number: ADC3664 Other Parts Discussed in Thread: ADC3644 Hello,
I am bringing up the ADC3644 in its default configuration and operating it in 14-bit, 2-wire output mode as defined in the datasheet. As part of initial bring-up and interface verification…
Part Number: ADC3664 Tool/software: Hi support team,
I select ADC3664 as ADC for my design with sample rate is 80MSPS. The input signal like the attached image. it likes a pulse with frequency 40MHz. (maximum). I read in the datasheet and it mentions…
Part Number: ADC3664-SEP In reviewing the ADC3664-SEP SEE Test Report I note that SET consideration has only been applied to DCLK events. I'm interested in the SETs as applied to conversion error and DDC/NCO SET characteristics. The DDC/NCO is a relatively…
Part Number: ADC3664 Hello,
I'm trying to use the avaluation board ADC3664EVM,
and therefore to program ADC modes using commands or a configuration file,
As you can see in the SPI transaction figure, my settings, but how do I write these low level…
Part Number: ADC3664-SEP Tool/software: I am looking at the ADC3664RSBTSEP analog to digital converter, and pin 27 is labeled as a no-connect.
I need to know if this part is internally connected to anything, or if it is just a floating pin
Part Number: ADC3664 Tool/software: Hi everyone,
I'm currently working on capturing raw data from my ADC and need to calculate the Vpp (Peak-to-Peak) of an input sinusoidal signal. My ADC setup is in its default mode. Could someone guide me on how to…
Part Number: ADC3664 Tool/software: I have a situation where 4 of the ADC3664 devices will be used in a design. The devices will operate from the same input clock source and are intended to be synchronous.
My question is: can the FPGA receiving the…
Part Number: ADC3664 Tool/software: Dear Technical Support Team,
I'd like to use six ADC3664 on the same board and it has four clks.
Do you have any idea to reduce or sharing clocks?
CLK (in )
DCLKIN(in)
DCLK(out)
FCLK(out)
According…