Part Number: ADC3683 Tool/software: The supplied 20-bit_Configs.txt file defines SPI writes for configuration. The question is if ther is a way to load that file through the ADC35xx_EVM_GUI? The program has a Python script load facility, but I'm not sure…
Part Number: ADC3683-SP Other Parts Discussed in Thread: ADC3683EVMCVAL Tool/software: Hello,
We are interesting to implement this ADC in our prototyping board.
For that, we need to access of the sources mentioned in the document "SBAU446 EVM User's Guide…
Part Number: ADC3683-SP Tool/software: Hello,
I have two questions regarding the amplitude of the sampling clock signal.
We want to drive the sampling clock signal with an FPGA. Since we have a few inches of trace between driver and receiver, we need…
Part Number: ADC3683 Dear TI Team,
in the datasheet it is written that Jitter on DCLKIN must not be higher than +/-50ps. In our design the ADC sampling clock and the DCLKIN clock will be frequency-aligned driven by FPGA. However, compliance to the +…
Hi Rob,
Thank you so much for the reply. There's a little bit difference between this appnote & real usage.
We didn't use cross two channels. We are using 2*ADC3683s sampling signals independently. There are 4 channels in total between the two…
Part Number: ADC3683 We are attempting to improve the INL performance of the ADC3683 by using code correction techniques. In our measurements we generally see a greater INL magnitude than reported as typical in the ADC3683 datasheet and also variance…
Part Number: ADC3683 Due to clock distribution constrains in my design I would like utilize 20-bit output formatting in all modes: By-pass, real, complex (NCO is active). 1 wire connection is preferred. Acc. the datasheet is possible, but evaluation SW…
Part Number: ADC3683 Hello，
One customer used ADS3683 and wanted to configure the Decimation Bypass, 1-wire, 16bit mode, below is the configuration, but the FCLK duty cycle is not 50%.
I found the 0x20~x022 has no problem and 0x1B =0x88, I wonder why the…
Part Number: ADC3683
Hi TI Expert,
I need to design a optical detector with wide dynamitc range so the input voltage to the AIN_P may be very large, for instance 3.4V.
And I notice that when the AIN_P is large and clamped by the the ADC's internel diode…
Part Number: ADC3683 Hi, When I enable test pattern and enable digital bypass, I can see the test pattern in my FPGA debugging environment. But with bypass disabled. There is no test pattern anymore, just raw ADC data (same with test pattern off and digital…
