Part Number: ADC3910D125 hi sir
we survey the TI parts. need to check below SPI process if correct
Set Address 0X00 bit[7] 1
Set Address 0X89 bit[5] 1
Set Address 0X484 bit[1] 1
Set Address 0X4BF bit[1:0] 3
thanks
Part Number: ADC3910D125 Hello Team,
Hi,
After hours of trying and reading the datasheet, I cannot figure out why 2X oversampling is not enabled for analog data. I can enable it for the test pattern generator, but when I try to enable it for analog…
Part Number: ADC3910D125 Hi Team,
Posting on behalf of our customer.
I'll share this E2E post with our customer so he can reply when needed.
I am investigating the datasheet of ADC3910D125. At the beginning, it is written that the ADC has 10 bits…
Part Number: ADC3910D125 Tool/software: We plan to use ADC3910D125 in combination with an FPGA. We will not use the on-chip digital down converters. We only want the raw output into the FPGA and to any decimation+filtering there. The chip has a 12 bit…
Part Number: ADC3910D125 Tool/software: Hi team,
The datasheet says NC pin should be connected to GND. Is it correct and does it means the NC pin shouldn't be floating?
There's typo for NC pin number in this table and the there's no connection…
Part Number: ADC3910D125 Hi,
I am trying to figure out what DCLKIN is in datasheet SBASAD1A-Revised MAY 2024
In the block diagram on page 1, you have listed these three signals:
DCLKIN
DCLK
nDCLK/FCLK
In Table 6-1 on the same page, you have…
Part Number: ADC3910D125 Tool/software: Hi team,
Could you explain which one is correct?
NC is pin 5 and VREF is 17 show as Figure 4-1
But table no pin5 and pin17 both REF and NC function.
also ADC3910D125EVM pin5 is DCLKIN different with datasheet…
Part Number: ADC3910D125 Tool/software: Hi!
I'm thinking of using the ADC3910xxx.I noticed it has high Z input buffers. I also noticed that the analog inputs have a Vcm requirement of 1.25V. Therefore, I need to drive a differential signal, with Vcm…
Part Number: ADC3910D125 Tool/software: On the ADC3910D125EVM schematic page 4 there is a PIN CONTROL circuit that pulls SEN/M0, SCLK/M1 and SDIO/M2 down (as well as the OEN line). And there is the J5 header, perhaps to allow the option to pull any of…
