Part Number: ADS1251 Hi team
According to Figure 12, DOUT/DRDY goes to low level after the LSB output. Does the pin always go to low level after the LSB output even if the LSB is high or low?
Part Number: ADS1251 Hi team,
The datasheet mentions below. What will happne if some digital or analog input pins not are low level?
Regards,
Noriyuki Takahashi
Part Number: ADS1251 Other Parts Discussed in Thread: ADS127L11 Tool/software: The datasheet states that the nominal CLK and SCLK input voltage is 0.6V, but doesn't specify a min or max allowable. If I had a microcontroller deviate from normal configuration…
Part Number: ADS1251 Hi team,
Could you tell the max junction temperature of ADS1251?
Is this 150 degree C or 100 degree C as the datasheet mentions?
Regards,
Noriyuki Takahashi
Part Number: ADS1251 Other Parts Discussed in Thread: ADS127L11 Hello,
In the ADS1251 datasheet, it mentions that the frequency reponse can be calculated with a spreadsheet from TI, "SBAA103, A Spreadsheet to Calculate the Frequency Response of the…
Part Number: ADS1251 Hello,
I'm hoping for a hint on where to look when on a board, both of the installed ADS1251 would always clock out the value 80000000h for positive saturation, regardless of the signal input to the ADCs.
The scope screenshot…
Part Number: ADS1251 Dear Team,
A related question to: e2e.ti.com/.../ads1251-sigma-delta-switching-frequency-synchronization
"Since I am using 100% of FPGA pins, I am summing clock,serial clock, the same for all chips. And just MISO pins will be…
Part Number: ADS1251 Hi Team,
I am trying to help my customer with the following question. Can you offer any advice?
"In my design I have a high voltage flyback transformer that will generate most of the noise. I will sync switching frequency with…
