Hello Shaii,
You should be able to drive 5 ADS127L01 plus FPGA with a single ADS127L01, provided that the board capacitance is not too high and the devices are close together. Each ADC digital input will have about 2pF of capacitance and the SCLK/FSYNC…
Part Number: ADS127L01 Hi,
Setup:
Format SPI Mode
High Performance Mode
OSR = 32
Filter Wideband Band 1
Vdd, AVdd = 3.3 V, AGND placed to common ground plane
fsmode (1k gnd), format (1k gnd), reset (1k pull-up)
we encounter a strange…
Part Number: ADS127L01 Other Parts Discussed in Thread: LAUNCHXL-CC26X2R1 ,
Hi all,
I want to connect one ADS127L01 to my LAUNCHXL-CC26X2R1 through SPI. At first, I want just read registers in ADS127L01 to test SPI connection. (ID register at address…
Part Number: ADS127L01 Other Parts Discussed in Thread: TIDA-01471 Dear Technical Support Team,
CCLD and IEPE are called differently, but are they the same? Can the circuit of TIDA-01471 be used for CCLD as it is? Please let me know if you have any…
Part Number: ADS127L01 Other Parts Discussed in Thread: TIDA-01471 , Hi,
I have any questions.
1. Please tell me the reason why R2, R3 and R4 described in "Schematic" of TIDA-01471 are connected.
https://www.ti.com/tool/TIDA-01471
If the reason…
Part Number: ADS127L01
Tool/software: TI C/C++ Compiler
we are using ADS127L01 and raspberry pi B3 in our design for a DAQ measurement system. The ADC works is working fine but in Some reading up the device is reading constant value 7FFFFF irrespective…
Part Number: ADS127L01 Hi,
Please is it possible to daisy chain 2 ADS127L01 in frame sync slave mode at 512kHz samplerate? The datasheet specifies min. period of SCLK at 40ns which is 25MHz - enough for 384kHz (64bits per frame period). 512kHz requires…
Part Number: ADS127L01
We run three of these ADCs in sync with each other, on the same CLK signal. Picture 1 shows how each ADC is wired (they are all identical). Strange intermittent readings from the ADCs were what started me on this investigation…
Part Number: ADS127L01
Issue:
With the HR pin tied low, when converting the EXT terminal external resistance from 120K to 60.4K, that is, when switching VLP mode to LP mode, it does get higher in power consumption, but the output noise of the ADC…