Hi Jim,
James Apperley said: I hope you can help me understand the specs from a time domain standpoint. Since we are using the ADS1282-SP in a snapshot mode with dc signals that are being multiplexed to the input. As you will see below we only take one…
Part Number: ADS1282-SP Other Parts Discussed in Thread: ADS1283 Hello,
I am acutally doing the worst case to analyze what will be the DC offset due to the input bias current from the ADC.
The input bias current in the datasheet which is 1nA represent…
Part Number: ADS7953 Other Parts Discussed in Thread: ADS1278-SP , ADC128S102QML-SP , ADS1282-SP Hello,
Is there a space version of your ADS7953SBDBTR? If not, is there another 16-ch 12-bit part that is space rated?
Thanks, Adam
Part Number: ADS1282-SP Hello team,
my customer is running the device in high resolution mode with 5V on AVdd and 3.3V DVdd and has the following questions.
1) What is the absolute max power dissipation the part can handle? The spec shows power dissipation…
Part Number: ADS1282-SP The datasheet provides a typical bias current value of 1nA (up to 125C). A max number is needed for a WCA - do we have any guidance for a max number?
Do we have any post-radiation data from the TIS testing that we can share - I…
Hi,
Is there any reason you didn't evaluate the ADS1282-SP using the ADS1282EVM-CVAL which has a space grade prototype device on it as well as space grade LDO's to power the board. This EVM mounts to an MSP430FR5969 launchpad EVM for data collection…
Part Number: ADS1282-SP hi, I have some confusion about the default mode of the device. Section 8.5.1.5 of the datasheet indicates that the device is in read data continuous mode by default. but figure 63 indicates that the default sync mode is pulse…
Part Number: ADS1282-SP (assuming Chris Hall is answering)
hi Chris, I'm having some trouble understanding the timing when in pulse-sync mode, specifically Tdr.
assuming that Fclk=3.125MHz and Sclk=1.5625MHz:
once I assert the SYNC pin, DRDY goes…
