Hi KIRYOUNG YANG,
If your external clock to the ADC is 8.192MHz, the default data rate is 4-ksps with the default 1024 OSR. Please double check and let me know whether your interval of the /DRDY signal is 250us or not.
BR,
Dale
Part Number: ADS131M04 Other Parts Discussed in Thread: ADS131E04 Tool/software: We are currently in a cost reduction phase of the project and would like to replace the ADS131E0x with the ADS131M0x. Unfortunately we haven’t been able to reproduce the…
Part Number: ADS131M04 Other Parts Discussed in Thread: SYSCONFIG Tool/software: We are able to read only ADC channel data and its status. But we are not able to read and write its configuration registers. Also when we send 0x0 command, does it consist…
Hi Aleyna,
thanks a lot for the positive update. That sounds good.
I still struggle to understand all your connections to be honest. Previously you also mentioned some connections on JP1. I would probably need a drawing or mark-up in the schematic to…
Hello Sumeet,
I responded to your simulation questions on the private chat.
Yes, the ADS127L18 requires a 1.8V IOVDD supply, and the processor connected to it must either support 1.8V IO levels, or voltage level translators must be used.
Regards, Keit…
Part Number: ADS131M04 Tool/software: Hi Team,
When we are doing a BCI test, insert interference to the AD sample side, we found the SPI read back from ADC is not correct. At this stage, we only started to configure the ADC, so only write and read the…
Part Number: ADS131M04 Tool/software: in given image blue pulse is clock(4Mhz) and red is DRDY. currently we not doing SPI communication only give clock input at CLKIN pin. at that time DRDY pin stay low and after some time its goes high, but as per…
Part Number: ADS131M04 Tool/software: Hi team,
my customer is using ADS131M04 with default setting, changed OSR and measure the DYDR output.
CLOCK[OSR] = 011b，DRDY output frequency is 4K
CLOCK[OSR] = 010b， DRDY output frequency is 8 K 输出频率8K
CLOCK[OSR] …
