Part Number: ADS131M08 Hi team,
For the source-termination resistor placed at the clock buffer, do you have any specific value suggestions or reference design?
Thanks!
Regards,
Ivy
Part Number: ADS131M08 Hi, Dale Li:
I read your post ADS131M08: Simultaneous sampling ADC selection for strain measurements .
What about the 300K differential input impedance on ADS131M08? Does it affect the bridge measurement?
Thanks.
-WQ
Part Number: ADS131M08 The datasheet for the ADS131M08 (SBAS950B Oct-2019 / revised Feb-2021) lists THRSHLD_LSB (reg 0x08) on page 47 as only having the RESERVED[7..4] DCBLOCK[3..0] bitfields, and not the CD_TH_LSB[7..0] bitfield. The register details…
Part Number: ADS131M08 Hi Team,
My customers are evaluating the ADS131M08 to sample the voltage of testing battery. During the temp-drift tests they put the ADS131M08 to 25 degree C circumstances and 45 degree C circumstances and compare the sampling…
Other Parts Discussed in Thread: ADS131M08 Hi,
Actual I am developing an application where I required to use ADS131m08 so I have few questions
1. if we are using a separate controller like STM32 or any other do we need to give digital clkin signal if…
Part Number: ADS131M08 Other Parts Discussed in Thread: TMS570LC4357 I am working on interfacing with two ADS131M08 devices using a TMS570lc4357 (SPI1) and having some odd behavior on the MISO lines. The design is configured so that it uses MibSPI parallel…
Part Number: ADS131M08-Q1 Other Parts Discussed in Thread: ADS131M08 Hello,
We are trying to achieve a wider FSR with the ADS131M08-Q1. We see that in the datasheet, the maximum recommended voltage for REFIN is 1.3V, though the pin is rated to AVVD + 0…
Part Number: ADS131M08-Q1 Other Parts Discussed in Thread: ADS131M08 Hi team,
The attachment is the schematic diagram of the customer's ADS131M08. Please help to check, the chip part, the customer's library is not completed, and a 32PIN is used instead…
Part Number: ADS131M08
Hello,
I noticed the following in the datasheet:
Can you elaborate on the reason why the Master Clock needs to be synchronous with the SPI interface clock (SCLK)? It does not appear that the EVM is following this requirement…