Other Parts Discussed in Thread: ADS4125 Hello, our company has a mass-produced product using ADS4125 IRGZT;The instrument is a hand-held measuring instrument.
This is how the instrument works:The signal of the sensor is conditioned, converted by ADS 4125…
Part Number: ADS4122 Other Parts Discussed in Thread: ADS4142 , ADS4125 , ADS4145 Hi,
ADS4122 data sheet (SBAS 520 C) page 13 Analog Power ADS4122, ADS4142 (125 MSPS): 112 mW It is stipulated in.
The ADS4122 and ADS4142 are specified with 65MSPS. (page4 5…
Nhi,
We can offer the following LVDS devices:
Speed (Msps) bits Part # # of Converters
125 12 ADS4125 1
125 14 ADS4145 1
80 12 ADC3223 2
80 14 ADC3243 2
125 12 ADC3224 2
125 14 ADC3244 2
If you prefer JESD204B parts we can recommend these as well.
Regards,
Ji…
Part Number: ADS5482EVM Other Parts Discussed in Thread: TMDSEVM572X , , ADS4122EVM , ADS4122 , ADS4125 Hi TI'ers,
My requirement is i want one ADC evm 1.which can interface with the gp evm AM572x(TMDSEVM572x). 2.Sampling rate should be grater than 100MSPS…
Eric,
If you only need a single ADC, the ADS4122 (12bit, 65Msps) or ADS4125 (12b, 125Msps) parts would be a good option. If you need a dual or quad device, there are several options available from the ADC3xxx family, shown in the table below.
Regards, …
Other Parts Discussed in Thread: ADS4125 Hi,
I am just trying to track the pins of FPGA used to interface with ADS4125EVEM.
I am surprisingly finding that, TRUE o/p of ADS4125 is connected to COMPLEMENT i/p of FPGA.
Example:
Differential
ADS4125
…
Hi Matt,
Returninmg back to this post !!!
I have designed an anti-alising filter similar to circut given in slea085.pdf (Application Report SLEA085 TVP5146 Anti-Aliasing Filters). Almost similar circuit is designed except inductor taken with 1.2 uH. With…
Other Parts Discussed in Thread: ADS4125 , ADS4145 Hello,
We have been looking for >= 100MSPS ADC and with input range between 0 -5V.
What are our options?
Thank you.
Hi,
From my reading of the datasheet, the data typically becomes valid 9ns after the sample clock and the rising edge of DV is typically 10ns after the sample clock. Or looking at the max numbers, the new data becomes valid by 11ns max after the sample…