Part Number: ADS4149
Hi,
I am using ADS4149 ADC in our custom board. The ADC sampling clock is driven from FPGA.
Sampling Frequency(Fs) = 24MHz
ADC input Signal Frequency(Fin) = 328MHz
ADC input signal power level = -10dBm.
FPGA Part Number : MPF200…
Part Number: ADS4149 Other Parts Discussed in Thread: ADC3542 , ADS4146 Hi,
We are using ads4149. The adc input signal frequency range is 328Mhz to 335Mhz. I am planning to use 24mhz as sampling frequency, by considering the input bandwidth of 7Mhz.
For…
Part Number: ADS4149 Hello,
We are using hardware which implements a 208 MHz LVDS DDR data interface between the ADS4149IRGZT and an FPGA. We have a version of the board which was only modified by skewing phase by 80 ps on the input data clock. We now…
Hello Jainendra,
ADS4149 requires a pretty low input common-mode voltage of 0.95V. The schematic you shared shows that you are setting the VCM of the THS4541 to 0.95ishV via voltage divider which is correct. However, do take note of decrease in distortion…
Part Number: ADS4149 Hi Team,
We would like to ask your help regarding our customer's inquiry below.
I am reviewing app note SLAA594A - June 2013 - Revised 2013. I have a question on section 3.1 (page 6) of this app note. Question: what happens to…
Part Number: ADS4149
The serial interface register map of ADS4149 is given in the datasheet SBAS483G Table 10, are there any other registers that are not specified in the datasheet?
Part Number: ADS4149
Based on the IBIS model of ADS4149, we decided to use the CMOS_DATA_HIGH1 buffer.
How should we set the register bits (in the address 41h) in order to use the CMOS_DATA_HIGH1 buffer settings? Does this correspond to CMOS CLKOUT STRENGTH…
Part Number: ADS4149
The ADS4149 datasheet describes the HI PERD MODE 2 bit as:
Bit[0] HI PERF MODE 2: High performance mode 2 This bit is recommended for high input signal frequencies greater than 230MHz. 0 = Default performance after reset 1 = For best…
Part Number: ADS4149 Hi.
regarding ADS4149:
- In the data sheet pin 23 is marked "reserved". Is it ok if I connect it to GND? - In my application I will use 4x ADCs, the ADCs are directly connected to the FPGA. What do I need the "Output Clock…