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  • ADS41B49: DDR connection

    TI Thinks Resolved
    Part Number: ADS41B49 Hi E2E, Good day. Can we write directly into DDR memory without the need for an FPGA? Our customer would like to capture a signal at 250MSPS during 10miliseconds then process it with a microcontroller then send the results through…
    • Answered

  • ADS41B49: ADS41B49 datasheet (INP/INM absolute max and signal voltage range at input of 1.7V + 0.375V, VCM voltage)

    Resolved
    Part Number: ADS41B49 Other Parts Discussed in Thread: ADS42B49 I saw some threads about the absolute max for INP and INM. AVDD being between 1.7 and 1.9, 1.9V will always be an absolute max of 1.9V : max = minimum(1.9V, AVDD + 0.3V) But what about the…
    • Resolved
    • Answered

  • ADS41B49: How to choose 12-bit adc and 14-bit adc

    Resolved
    Part Number: ADS41B49 Other Parts Discussed in Thread: ADS41B29 Usually, the high-order adc is selected to obtain a higher effective number of bits and a better signal-to-noise ratio. However, in the actual selection process, the dynamic indicators of…
    • Resolved
    • Answered

  • ADS41B49: No output clock and no SPI readback

    Resolved
    Part Number: ADS41B49 We are in the DVT process with a new board and are not able to get a high-speed differential clock output nor a SPI readback from the ADS41B49. 1. Output clock issue: We have a 192 MHz differential clock present at CLKP/M as driven…
    • Resolved

  • How to display sinusoidal in computer screen by ADS41B49 ?

    TI Thinks Resolved
    Step Recorded.docx CLK(1M).Input(98k).xls CLK(1M).Input(250k).xls CLK(1M).Input(750k).xls CLK(1M).Input(505k).xls CLK(1M).Input(998k).xls

  • ADS41B49: Test clock pattern forADS 41xx/58B18/58B19 EVM Software control

    Part Number: ADS41B49 Hlo all, I have use the ADS41B49 evaluation board for my project.In this, how can I access the Toggle Clock pattern in the above software or else give addvise regarding the the register mapping in it.

  • ADS41B49 absolute maximum ratings

    Hello Team, please clarify the MAX value for INP and INM. Wouldn't it make sense to specify it from -0.3V to AVDD_BUF + 0.3(or 0.6)V? Why 1.9V? Where does this come from, please? Thanks and Best Regards, Hans
    • Answered

  • ADS41B49EVM: Reference HDL Design

    Resolved
    Part Number: ADS41B49EVM Other Parts Discussed in Thread: ADS41B49 , FMC-ADC-ADAPTER , I am interfacing an ADS41B49EVM to a Zedboard (Zynq-7020) with the FMC-ADC-ADAPTER. I am looking for any reference HDL for interfacing to the parallel DDR LVDS outputs…
    • Resolved

  • ADS41B49 data plots

    Other Parts Discussed in Thread: ADS41B49 Hello TI, My customer is considering using the ADS41B49 A/D converter on an upcoming design. He is skeptical about some of the data in the datasheet. Specifically, he's hoping that the 12-bit data/plots are accurate…
    • Answered

  • ADS41B49 control Interface

    Resolved
    Other Parts Discussed in Thread: ADS41B49 Hello, Even not explicitly said, but the ADS41B49 control interface looks like SPI interface, can I use a SPI interface to control it? Thanks. Cero
    • Resolved

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