Part Number: ADS42LB49 Other Parts Discussed in Thread: ADS42LB69EVM Hi,
I download design file of ADS42LB69EVM from TI website. However, there are no brd file in these files.
Can you please share the .brd file of the Rev D for our reference.
Best reg…
Part Number: ADS42LB49
Hi, We have encountered problems with signal integrity on ADS42LB49 and its QDR LVDS interface. The ADC is connected to FPGA (Ultrascale+) with internal 100ohm terminations on LVDS input buffers, the clock we used for the ADC is…
Other Parts Discussed in Thread: ADS42LB49 , ADS42LB69 Dear Sir/Madam,
As per datasheet 8.3.5: Output Data Format
FFor a positive overdrive, the output code is 3FFFh for the ADS42LB49 and ADS42LB69 in offset binary output format; the output code is 1FFFh…
Hi Sirui,
In the table below are three HS ADCs that may work for your customer. These ADCs do not have >77 SNR, but customer could use any of these devices and sum the two channels together to increase the SNR by 3dB and meet the SNR requirement.
…
Other Parts Discussed in Thread: ADS42LB49 Hi,
ADS42LB49 Unused pin processing
In the dual channel ADC, for example when B-ch is not used, Analog input terminals (INBP, INBM) of Bch, and Digital Output terminal (DBxP, DBxM, DBCLKP, DBCLKM, DBFRAMEP, DBFRAMEM…
I am looking to reduce power so I'm looking for a version of ADS42LB49IRGCT, preferably same footprint, that consumes lower power or if there is an app note that will allow it tor run at lower power.
Thank you,
Mauricio Solis
Other Parts Discussed in Thread: ADS42LB49 Hello, The customer would like to use ADS42LB49 with 93.3C of Tj(max). Could you please let me know the parameter which the parameter specification will be worse with this Tj(max) ? Best Regard, Ryuji Asaka
Part Number: ADS42LB69 Other Parts Discussed in Thread: ADS42LB49 ,
Hi,
Good Day.
Customer don't know how to calculate output data code.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive…
Hi,
I will use 2 ADC42LB49 in my design and synchronization is very important for me. I am planning to using a clock generator and a clock buffer(LVPECL) to drive ADCs. Considering both timing and performance; do you advise me to use a 250 MHz clock as…
Other Parts Discussed in Thread: ADS42LB49 Hi
I couldnt see any information about the clock (clkin) to output (dx[15:0]) delay time in the datasheet. Can you inform me for this?
Another question is that how can I download the IBIS or AMI models of the…
