Part Number: ADS42LB49
Hi, We have encountered problems with signal integrity on ADS42LB49 and its QDR LVDS interface. The ADC is connected to FPGA (Ultrascale+) with internal 100ohm terminations on LVDS input buffers, the clock we used for the ADC…
Part Number: ADS42LB49 Other Parts Discussed in Thread: ADS42LB69EVM Hi,
I download design file of ADS42LB69EVM from TI website. However, there are no brd file in these files.
Can you please share the .brd file of the Rev D for our reference.
Best…
Part Number: ADS42LB49 Hello,
I am using channel A with sampling rate of 200 MHz and in DDR mode, I want to power down channel B since I am not using it and noticed the following in the datasheet:
Does this mean I cannot power down channel B when…
Part Number: ADS42LB49 Other Parts Discussed in Thread: CDCE62002 Hello,
I am working on a design and planning to use ADS42LB49 at 200 MHz sampling rate.
I though about using CDCE62002 as clock source, but the jitter seems a bit high for the ADC…
Other Parts Discussed in Thread: ADS42LB49 Hi,
ADS42LB49 Unused pin processing
In the dual channel ADC, for example when B-ch is not used, Analog input terminals (INBP, INBM) of Bch, and Digital Output terminal (DBxP, DBxM, DBCLKP, DBCLKM, DBFRAMEP…
I am looking to reduce power so I'm looking for a version of ADS42LB49IRGCT, preferably same footprint, that consumes lower power or if there is an app note that will allow it tor run at lower power.
Thank you,
Mauricio Solis
Other Parts Discussed in Thread: ADS42LB49 Hello, The customer would like to use ADS42LB49 with 93.3C of Tj(max). Could you please let me know the parameter which the parameter specification will be worse with this Tj(max) ? Best Regard, Ryuji Asaka
Other Parts Discussed in Thread: ADS42LB49 Hi
I couldnt see any information about the clock (clkin) to output (dx[15:0]) delay time in the datasheet. Can you inform me for this?
Another question is that how can I download the IBIS or AMI models of…
Other Parts Discussed in Thread: ADS42LB49 Hello,
I am currently working on interface for ads42lb49 ADC (Xilinx fpga), and I am having problem with understanding SYNCIN pin.
Configuration of adc:
- QDR mode
- 200 MHz clk into ADC (200 MSPS), no…
Hi,
I will use 2 ADC42LB49 in my design and synchronization is very important for me. I am planning to using a clock generator and a clock buffer(LVPECL) to drive ADCs. Considering both timing and performance; do you advise me to use a 250 MHz clock…
