Hi again,
Thanks for your response. After some testing, it seems that this ADC lane is broken. We tried another board (same design) and it works. We are in a redesign phase and we manipulated the board so the ADC was probably damaged in the process.
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Part Number: ADS42LB69 Tool/software: Hello,
Can someone please help me understand about the TEST PAT ALIGN field in register 8 of ADS42LB69?
As I understand it, writing 1 to the TEST PAT ALIGN field will synchronize the phase of the test pattern of…
Hi Andrew,
Yes, you would need to route all frame and data clocks from each ADC device to the FPGA in order to sync appropriately. Otherwise, there can be some variance. The data lines should be the same length as well.
If you can forward some schematics…
Part Number: ADS42LB69 Tool/software: Dear support Team,
I would like to know if you could provide some INL plots for this ADC, i.e at 70 MHz-250 MS/s?
Additionally, does TI have a design support Tool to calculate and plot INL from a sine-wave ADC data…
Part Number: ADS42LB69 Tool/software: Dear support Team,
I would know if it is possible to disable the internal dithering process using a control bit? If yes, would it be possible to use the internal DAC in DC mode for compensating the intrinsic ADC…
Part Number: ADS42LB69 Hi,
I am using ADS42LB69 in my design. Can you please provide the input SNR requirements for this ADC.
i.e If I want to give an input of -50 dBm to ADC, what is minimum noise level that can be present along with -50dBm signal.
…
Part Number: ADS42LB69 To whole it may concern,
As for t2 Reset pulse width of Table 8 in datasheet is 10ns to 1μs, if I input exceeding this width(ex.10ms) pulse width signal, is there a risk of malfunction?
As for usage, the reset signal is input…
Part Number: LMH6554 Other Parts Discussed in Thread: ADS42LB69 , , TINA-TI Dear Sir/Madam,
I am using LMH6554 amplifier in dc coupled configuration to drive ADS42LB69 whose VCM requirement is 1.9V.
The LMH6554 datasheet is mentioning split supply method…
Part Number: ADS42LB69 I'm working on project where I'm using ADC(ADS42LB69),16bit. I wanted to know how to change the sampling rate of the ADC, as per spec Min is 10MSPS and Max is 250 MSPS. And the input clock frequency used in my project is…
