Part Number: ADS42LB69 The datasheet only appears to give a typical value for the ads42lb69 lvds common mode output voltage.
Is data for the maximum and minimum value available?
Part Number: ADS42LB69 Other Parts Discussed in Thread: ADC3563
Dear Technical Support Team,
I'd like to comfirm read timing spec for SPI about ADS42LB69.
There is only read timing diagram.
Write timing has a spec like following "Table 9.…
Part Number: ADS42LB69 Tool/software: Hi,
We are using the ADS42LB69 to acquire a 250 MHz sinusoidal signal. I then demodulate the signal to obtain the IQ components using the direct sampling technique, where I sample the signal at 133.333 MHz, which…
Part Number: ADS42LB69 Tool/software: Hi team
Does this device have the recommendation of power-up sequence requirements?
If it has, could you tell the requirements?
Regards,
Noriyuki Takahashi
Part Number: ADS42LB69 Tool/software: Hello,
Can someone please help me understand about the TEST PAT ALIGN field in register 8 of ADS42LB69?
As I understand it, writing 1 to the TEST PAT ALIGN field will synchronize the phase of the test pattern…
Part Number: ADS42LB69 Tool/software: Dear support Team,
I would like to know if you could provide some INL plots for this ADC, i.e at 70 MHz-250 MS/s?
Additionally, does TI have a design support Tool to calculate and plot INL from a sine-wave ADC…
Part Number: ADS42LB69 Tool/software: I have two ADS42LB69s fed by the same clocks. ADCs are controlled by an FPGA. SYNCINs are not used. I am "calibrating" clock and data alignment of each ADCs using IDELAYs and test patterns. However, I noticed that…
Part Number: ADS42LB69 Hi,
I am using ADS42LB69 in my design. Can you please provide the input SNR requirements for this ADC.
i.e If I want to give an input of -50 dBm to ADC, what is minimum noise level that can be present along with -50dBm signal…
Part Number: ADS42LB69 Tool/software: Dear support Team,
I would know if it is possible to disable the internal dithering process using a control bit? If yes, would it be possible to use the internal DAC in DC mode for compensating the intrinsic ADC…
