Part Number: ADS5294 Tool/software: Are there any specific power sequence requirements? I have inherited a design where AVDD and LVDD are supplied from separate regulators with a programmable delay (currently time together). At present, I have a board…
Part Number: ADS5294 Hi,
We are using an analog to digital converter ADS5294IPFP. The designer connected both pins of a channel together as in the picture included. He did that to measure the intrinsic noise for a single channel. My questions is what…
Part Number: ADS5294 Tool/software: During testing, LVDD was inadvertently set at 0.274V for approximately 1 hour with all other inputs and outputs at nominal voltage levels. Is it possible that this could have stressed the ADS5294 in any way?
Part Number: ADS5294 Hello all,
I work with the ADS5294 (own FMC board) and use timing diagram according to Figure 4. Enlarged 1-Wire LVDS Timing Diagram (14 bit) from DataSheet.
My FPGA project was based on dedicated deserializer ISERDESE2 of Xilinx…
Part Number: ADS5294 Other Parts Discussed in Thread: THS4509 ,
Tool/software:
Hello,
I want a ADS5294 internal Input circuit simulation model for my design reference as i'm using a THS4509 part for this to see the output for as a testing purpose…
Part Number: ADS5294 Hi,
We are testing ADS5294 noise floor and have observed SPUR as shown below.Test Set up :
Sampling rate of ADC: 60 Msps,
No input fed to ADC .(Input connector open )
Band of interest is 10 Mhz and a spur is observed at 10…
Part Number: ADS5294 Are all of the digital inputs
PD
RESET
SCLK
CSZ
SDATA
SYNC
compatible with 2.5 V logic level signals (i.e., with outputs from FPGA pins configured as LVCMOS25)?
Part Number: ADS5294 Hi,
We are using single device ADS5294, no decimation. Our sampling frequency is 10Mhz, 2-wire mode.
We want to output a single pattern.
We did the experiment with external sync: Steps we followed:
1. Soft RST( configure registers…
