Part Number: ADS5294 Tool/software: Are there any specific power sequence requirements? I have inherited a design where AVDD and LVDD are supplied from separate regulators with a programmable delay (currently time together). At present, I have a board…
Part Number: ADS5294 Hello all,
I work with the ADS5294 (own FMC board) and use timing diagram according to Figure 4. Enlarged 1-Wire LVDS Timing Diagram (14 bit) from DataSheet.
My FPGA project was based on dedicated deserializer ISERDESE2 of Xilinx…
Part Number: ADS5294 Other Parts Discussed in Thread: THS4509 ,
Tool/software:
Hello,
I want a ADS5294 internal Input circuit simulation model for my design reference as i'm using a THS4509 part for this to see the output for as a testing purpose…
Part Number: ADS5294 Hi,
We are testing ADS5294 noise floor and have observed SPUR as shown below.Test Set up :
Sampling rate of ADC: 60 Msps,
No input fed to ADC .(Input connector open )
Band of interest is 10 Mhz and a spur is observed at 10…
Part Number: ADS5294 Are all of the digital inputs
PD
RESET
SCLK
CSZ
SDATA
SYNC
compatible with 2.5 V logic level signals (i.e., with outputs from FPGA pins configured as LVCMOS25)?
Part Number: ADS5294 Hello,
I want to use the Ramp Pattern of ADS5294.
What registers do I need to configure and set up for this purpose?
I have configured it with 14-bit resolution, 1-wire communication, and LSB first as the default settings. …
Part Number: ADS5294 Tool/software: Hi,
I plan to use the ADS5294 to perform the acquisition of a high speed analog image sensor, and I need some help understanding the implication of the aperture delay specification.
My sensor is outputing a new…
Part Number: ADS5294 Hi,
We are using single device ADS5294, no decimation. Our sampling frequency is 10Mhz, 2-wire mode.
We want to output a single pattern.
We did the experiment with external sync: Steps we followed:
1. Soft RST( configure registers…
