Part Number: ADS5444-EP Tool/software: To reduce power consumption, I'd like to gate power to the ADCs when they aren't in use. Can I disable the 5V analog supply to the ADS5444-EP but leave the digital power domain (3.3V) enabled without damaging the…
Part Number: ADS5444 Good morning,
I am having trouble understanding why I am seeing a different values for my SNR, SINAD and SFDR measurements every time I capture data. The jumps are about plus minus 10db.
I am using an ADS5444SP Rev B EVM connected…
Part Number: ADS5444-EP Hi,
I need an ADC with a resolution of 10 bits. I think leaving the 3 Less Significant Bits output ports disconnected to use the ADS5444-EP. Could you tell me the evolution of its power consumption with the number of exploited…
Part Number: ADS5444-SP Other Parts Discussed in Thread: ADS5444 Hi, Good day. I hope you are doing well. We are looking for the IBIS model for the ADS5444-SP. We have noticed that the has an IBIS model. Can we use that instead? Looking forward to your…
Part Number: ADS5444-SP Hi Team,
We are currently using the TI 5962-0720701VXC for one of a hi-rel application. We would like to confirm if the +/- 0.6 %FS Offset Error specified in the datasheet is guaranteed by testing or analysis. If by analysis…
Part Number: ADS5444 Hello
As i decide to capture converter data with xilinx spartan 6 family for initial tests, i wonder is it possible to clock the converter with lvds clock outputs of sp6 family?
I searched and found some contradictory information…
Part Number: ADS5444-SP Hello team,
We have a design using the ADS5444-SP clocked at 125MHz. As the datasheet is spec’d at 250MHz we are working through how this effects a lot of the timing in the system.
We understand that (assuming a 50/50 duty…
Hi Aseok,
1. The nominal clock amplitude required for ADS5444 is 3Vpp differential. Lower amplitude clock may degrade the ADC performance.
2. I am not sure how clean the clock from FPGA will be. The quality of you clock signal will also affect ADC…
