Part Number: ADS5483
Dear Sir,
in the "Clock Inputs" section of the relevant datasheet, appears that the clock signals are referred to as analog GND and VDD (despite it seem to be digital signals), thus I have connected my pullup/pulldown resistors to…
Part Number: ADS5483 Dear Sir,
I use the TSH4130 FDA to provide the ADC input. The ADC works in external reference mode. The Vcm (3.1V typ.) is generated by the ADC and supplied to the FDA. The Vocm FDA input absorbs few hundred of uA (confirmed both…
Part Number: ADS5483 Hi,
I would like to repeat the same question because I can't find the answer anymore and I would like to make the question more precise, expanding it too. I have to define a schedule for the data flow from ADC. In a continuous…
Part Number: ADS5483 Hi to all,
I need to define a timing scheduling for the data flow from ADC. In a certain cycle of tens/hundred of ms I need to acquire data only for few ms (around 8-10 ms). Is possible to maintain reference voltage active and also…
Other Parts Discussed in Thread: ADS5483 , THS4509 Hi,
I recently got the ADS5483 EVM. I would like to use the Analog Input Option 2 with DC coupled signal. I followed the instruction for DC coupled operation at e2e.ti.com/.../1399346 - unsolder and resolder…
Other Parts Discussed in Thread: ADS5483 E2e,
We have a customer evaluating a ADS5483 using the TSW1400. When doing a data capture an error occurs which says "Read DDR to file time-out". How this be corrected?
Thanks for your help.
Regards…
Other Parts Discussed in Thread: ADS5483 Hello,
We have an ADS5483 on our pcb and I would like to know how we can detect if the ADC is saturated. I don't see any status signals on the part. Here's our signal flow in a few words: Antenna -> Mixer…
Divya,
Use a low noise clock source and follow the PCB layout guidelines I sent you in the previous post.
Regards,
Jim
6012.Clocking High Speed Data Converters - 3_17_2013.pptx
Xiaoqiang,
I would highly suggest not using the FPGA to clock the ADC as the FPGA output will have poor phase noise performance which will drastically lower the ADC performance. See attached document. If performance is not critical, Figures 161, 162 and…