Part Number: ADS54J40 Hello,
My customer wants to know the S2SO latency below for ADS54J40.
Q1. Is it correct to calculate the ADC Core Latency of ADS54J40 as below?
- Data Latency : 134 Clocks
- Decimation by 4, Using Mixer : 28 Clocks
-…
Part Number: ADS54J40 Tool/software: Dear,
My team is considering using ADS54J40 for our new project, interfaced with the JESD204B IP Core in Vivado.
For this, I was searching for an example design, and came across a Vivado 2016 version, which is…
Part Number: ADS54J40 Hi, Support
We are using two ADS54J40 on one circuit board and use two ADCs as slave, similar to the diagram below. The Xilinx FPGA board ZCU102 as the master device. The 1.8V HP bank has the SPI driver to drive the ADCs. In the…
Part Number: ADS54J40 In ADS54j40 datasheet analog input section, it states that the each input pin must be between VCM + 0.475V and VCM - 0.475V. Can you please let me know if the swing is over +/-0.475V, will it damage the ADC chip??
In the datasheet…
Part Number: ADS54J40 Other Parts Discussed in Thread: ADC3683 Hi, Support
The ENOB for ADSj40 is about 11.3 bits when Fin = 10MHz. If I need to digitize the signal at 50KHz or 100KHz, what will be the ENOB?
Is there a table for lower frequency…
Part Number: ADS54J40 Other Parts Discussed in Thread: THS7530 , , TINA-TI Hello,
I plan to use VGA, THS7530 in front of ADC, ADS54J40.
Please check if the circuit for connecting the output from the THS7530 to the ADC(ADS54J40) is correct.
The frequency…
Part Number: ADS54J40 Hello,
I'm designing a circuit using ADS54J40 and FPGA.
I want to verify that the clock and data connection for the JESD204B interface is correct.
And I want to get the schematic verification for the analog path connected…
Part Number: ADS54J40 Hi,
I hope that someone can help me with this issue we recently discovered.
We're using ADS54J40 in a DC-coupled design. We use only channel A, everything of channel B that we could disable is disabled. We have disabled VCM compensation…
Part Number: ADS54J40 Other Parts Discussed in Thread: LMK04828 Hello
I desghined like a below figure. Received clock Amplitude between PN pin is about 900mV(frequency is 737.28MHz) LMK04828 outputs LVPECL 1600mV when I removed both ac-coupled capacitor…
Part Number: ADS54J40 hi
I purchased a new analog to digital converter carte ADS54j40 I want to spin it in FPGA Kintex7, so I'm looking for the firmware of ADS54J40 to work with FPGA and process the output data of ADS54J40 in FPGA carte
thank you
