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  • ADS54J40: ADS54j40 input protection

    TI Thinks Resolved
    Part Number: ADS54J40 In ADS54j40 datasheet analog input section, it states that the each input pin must be between VCM + 0.475V and VCM - 0.475V. Can you please let me know if the swing is over +/-0.475V, will it damage the ADC chip?? In the datasheet…

  • ADS54J40: ADS54j40 ENOB

    TI Thinks Resolved
    Part Number: ADS54J40 Other Parts Discussed in Thread: ADC3683 Hi, Support The ENOB for ADSj40 is about 11.3 bits when Fin = 10MHz. If I need to digitize the signal at 50KHz or 100KHz, what will be the ENOB? Is there a table for lower frequency range…

  • ADS54J40: ADS54J40 : ADC analog input schematic

    TI Thinks Resolved
    Part Number: ADS54J40 Other Parts Discussed in Thread: THS7530 , , TINA-TI Hello, I plan to use VGA, THS7530 in front of ADC, ADS54J40. Please check if the circuit for connecting the output from the THS7530 to the ADC(ADS54J40) is correct. The frequency…

  • ADS54J40: Circuit verification for JESD204B Interface

    TI Thinks Resolved
    Part Number: ADS54J40 Hello, I'm designing a circuit using ADS54J40 and FPGA. I want to verify that the clock and data connection for the JESD204B interface is correct. And I want to get the schematic verification for the analog path connected to…
    • Answered

  • ADS54J40: about LVPECL input amplitude

    Resolved
    Part Number: ADS54J40 Other Parts Discussed in Thread: LMK04828 Hello I desghined like a below figure. Received clock Amplitude between PN pin is about 900mV(frequency is 737.28MHz) LMK04828 outputs LVPECL 1600mV when I removed both ac-coupled capacitor…
    • Resolved

  • RE: ADS54J40: Some ADS54J40 parts show regular offset jumps

    Antwan, I am closing this post as we are taking this offline with you. Regards, Jim
    • Answered

  • ADS54J40: General Registers address 0 read data

    Resolved
    Part Number: ADS54J40 Hello, We wrote data 0x81 at general registers address 0x0 and after that, read general registers data was 0x3c . but In datasheet,I can see bit [6:1] is all "0". so I am littlebit confused. Is this right action？
    • Resolved

  • ADS54J40: 4 lanes mode - signal on unused lanes

    TI Thinks Resolved
    Part Number: ADS54J40 Other Parts Discussed in Thread: THS4511 , ADS54J60 Hello, I have prototype board with ADS54J40 which is connected to the FPGA via FMC+ connector using 8 lanes. Unfortunately one of lanes is connected to wrong FMC+ pin so I am using…
    • Answered

  • ADS54J40: about unused input IN* pin

    Resolved
    Part Number: ADS54J40 hello Is it possible to float unused IN*P and IN*M pin ? or should I tied both pins to GND or Vcc? (I just want to use only 1ch.)
    • Resolved

  • ADS54J40: Conversion Error Rate

    Part Number: ADS54J40 Hello, What is the typical conversion error rate (CER) for the ADS54J40 ADC with 1 Gbps sampling? Is there a significant difference in CER between similar ADCs ADS54Jxx and resolution (12, 14, 16 bit)? Which 1 Gbps would you recommend…

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