Nir,
I think you may be confusing this part with a JESD part. This part either has 14 outputs per channel in CMOS mode or 7 differential pair outputs per channel in LVDS mode.
With the ADS54J42, the user could use this in one lane mode (LMFS = 1241…
Hello Derek,
Is the performance of 491.52MHz normal in the output clock plot of LMK04806?
I've received comments from another thread that the output clock phase noise could be an issue.
Please refer to the link below.
https://e2e.ti.com/support…
Other Parts Discussed in Thread: ADS54J42 , ADS58J63 Hello
I'm Alber as a FAE in Arrow Korea.
They have tested the mode as default in UserGuide(LMFS=8224) on evaluation board(ADS54J42EVM + TSW14J56)
My customer want to use ADS54J42 as setting LMFS…
Hi Dkkim,
Regarding your question on the test pattern:
Please refer to the another similar post here for reference. Jim did a great job explaining the expected test pattern: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters…
Anastasios,
If you plan on using H31 for SYNC, you must move the shunt on SJP3 from pins 2-3 to 1-2. By default, the ADC54J60EVM uses pins G12/G13 for SYNC. There are no signals connected to G2/G3. If you need a core clock for the FPGA you must use…
John,
We are getting to release an updated version of this data sheet which will correct for issues with the register map. Please take a look at the register map of the ADS54J42 (attached) as this is the most updated document and the ADS54J60 will be…
Bryan,
We are in the processes of revising all of the data sheets in this family to correct for mistakes, like the ones you mentioned. Currently, the ADS54J42 data sheet is the most up to date data sheet with regards to the register map and table 13…
Part Number: ADS54J42EVM Other Parts Discussed in Thread: ADS54J60EVM , ADS54J40 Dears.
We are considering developing the ADS54J42 .
We have ADS54J60EVM.
Please help me with the CFG file that can run JESD204B 4Line in ADS54JxxEVM.
We set it as…
Part Number: ADS5474 Other Parts Discussed in Thread: ADS54J42 , Here is the premise of my question:
Overview: I want deterministic sample collection after every power up. Here is an example scenario: Say that I power up the device and it initializes…
John,
Does your version of firmware use both a reference clock and core clock like the firmware Xilinx designed for us? If not, I am wondering if this may be the cause of some of your problems. The ADS54J42 uses the same core as the ADS54J60, and will…
