Part Number: ADS54J54 Hello,
Nowadays I debug the ADS54J54. The ADS54J54 works successfully. I test the SNR and ENOB of the ADS54J54. But there is the gap between the index on the datasheet to my test result. I want to know the test condition of the…
Part Number: ADS54J54 Hello,
I want to using external sampling clock which is generated by signal generator to evaluate the ADC performance in ADS54J54 EVM.
I can input 500MHz clock through SMA (EXT_ADC_CLK), but how to config other clocks such as the…
Hi,
There were no changes in the revised datasheet for things like max sample rate or lane rate. The changes were editorial in nature. There is a closely related device (ADS58J89) that has some extra features such as a trigger input to output full resolution…
Part Number: ADS54J54 Hello,
My customer has a question about ADS54J54 Total Latency.
[Q]
Please tell me the total latency of ADS54J54.
Is my understanding correct ?
<My understanding>
The total latency is ADC core latency and Link latency. (I referred…
Part Number: ADS54J54EVM Other Parts Discussed in Thread: ADS54J54 , , ADC12QJ1600
Hi,
We are currently in the process of designing a custom board that will incorporate either AMD's Virtex Ultrascale+ FPGA or Kintex Ultrascale+ FPGA , in addition to…
Part Number: ADS54J54
I'm using the Integrating ADC (QDC) to monitor the number of events, our set up is similar to the one in the picture. But how do we connect QDC to amplifier and Pulse generator, and how should we get signals form QDC to computer…
Part Number: ADS54J54 Hello,
My customer have some questions about SYSREF for ADS54J54.
[Background]
They want to use one-shot SYSREF.
It is written as follows in D/S.
P.28 : ADS54J54 device requires a minimum of 3 SYSREF pulses to complete the synchronization…
Hi Chase,
Thank you for your reply.
Does following software work for ADS54J54EVM + TSW14J57EVM?
SLAC624 — ADS54J54 EVM SPI GUI Installer v1.1
Best Regards,
ttd
Part Number: ADS54J54 Hello,
My customer has a question about ADS54J54.
[Q]
Does ADS54J54 transmit K28.5 character when JESD204B receiver (FPGA) set low on SYNCb pin before ADS54J54 receive SYSREF signal ?
Best Regards,
Hiroshi Katsunaga
Part Number: ADS54J54 Other Parts Discussed in Thread: LMK04828 , I use Xilinx FPGA connect to Ads54j54 via JESD204B, using LMK04828 as a clock chip. Now sysref and sync signals can be generated normally. From the IP CORE I can read status "link synced…