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  • RE: ADS54J60: Upper bits of lower byte inverted

    Doug, I would suggest trying different values for the elastic buffer delay (RBD) in your FPGA JESD IP Core. You may also want to increase the K value as well to allow for more lane buffering. The buffer release point in your FPGA may have been right on…

  • ADS54J60: temperature calibration Gain / IL

    Part Number: ADS54J60 Hello, IL correction does not perform well, if a low DC offset is given in Signal or intermitting small signal and large signal. We need to use frozen IL, DC coupling, random signal from customer, typ. 1Gsps. Is there a possibility…

  • ADS54J60: Residual content at 250MHz

    TI Thinks Resolved
    Part Number: ADS54J60 Residual frequency content left after signal has passed when capturing 250MHz tone. The ADCs are running at 1GHz. From the data sheet we understand there is a small residual tone at fs/4 from the interleaving technique but it is usually…

  • ADS54J60: Offset binary output setting

    TI Thinks Resolved
    Part Number: ADS54J60 Hello, Besides the two registers below, are there any additional registers a user needs to control for setting the offset binary of the ADS54J60? My customer has controlled the two registers, but they don't get the offset binary…

  • ADS54J60: DC offset correction block

    TI Thinks Resolved
    Part Number: ADS54J60 Hello, My customer is testing the DC offset correction block of the ADS54J60. Is there a way to normally operate the DC offset correction block with an external input signal through register control or H/W pin control etc? Thank…

  • RE: ADS54J60: ADS54J60

    Hi Nikitha, Kindly help me understand the comments that you have added on slide 4. There are two reference clocks to the FPGA: 1> The GT reference clock : Should be 122.88MHz (based on your xci) 2> The FPGA reference clock (sys_clock in the JESD IP…

  • ADS54J60: SYSREF Signal

    Part Number: ADS54J60 Hello, My customer is considering using the ADS54J60 under the following conditions. - CLKIN = 1GHz, LMFS = 4211, K=32, JESD204B = 10G According to SYSREF example in the datasheet, SYSREF is calculated as below. SYSREF = LMFC …
    • Answered

  • ADS54J60: required DC offset estimation time

    Resolved
    Part Number: ADS54J60 Hello, Related to the following E2E thread, I have one more question. (2) ADS54J60: idle channel input before the block is frozen - Data converters forum - Data converters - TI E2E support forums At least, how much time is required…
    • Resolved

  • ADS54J60: Inquriy about ADC input reference design

    TI Thinks Resolved
    Part Number: ADS54J60 Other Parts Discussed in Thread: TSW54J60EVM Hello, My customer is considering using the ADS54J60 to analyze about +/- 500mVp-p differential DC input signal as below. Positive & Negative dc input capture image(Yellow signal)…
    • Answered

  • ADS54J60: idle channel input before the block is frozen

    Resolved
    Part Number: ADS54J60 Hello, My customer is using ADS54J60 with DC-coupling input. In the datasheet 9.1.4.1, what does “idle channel input” mean? What kind of DC input signal should be used for the “idle channel input”? Or, ACD…
    • Resolved

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