Hi Richard,
Could you please provide me with the FPGA programming file for the ADS5517 EVM (Spartan-3E FPGA) that you mentioned in your original reply? The evaluation module is working fine, but I am unable to revert it to its stock configuration currently…
Part Number: TSW14J57EVM Other Parts Discussed in Thread: ADS4229 , ADS5517 , TIDA-00826 , TIDA-010128 , Hi -
I saw some previous threads on high-speed ADC design applications and I was wondering if someone could help me in picking out the right FPGA…
Other Parts Discussed in Thread: ADS5463EVM , ADS58B19 , ADS5517 , ADS5474 , HSMC-ADC-BRIDGE Hi,
I'm planning to use a DE2-115 to work with the ADS5463EVM, I have asked to Terasic about the speed of the HSMC and the say it can work at 640 MHz and that…
Hi,
In general, that list of ADC EVMs is meant to be the list of EVMs that are suitable for use with the HSMC-ADC-bridge into the Altera development platform. There is just one family of EVM on that list that I think we need to be careful of, and it…
Dear Richard,
Thanks for you instruction, the problem is solved.
As you said, it's a problem in the FPGA since the rising edge and falling edge of clock is not synchronized.
And also the data should be buffered at least for one clock otherwise…
ALB,
Is your EVM a Rev C board? If so I have attached the schematic. Please make sure all jumpers are set per the board photo I am sending. Take a scope probe (diff probe would be better) and monitor the ADC input across R21 and R26. You should see…
Jin,
The schematic looks good for the most part. Please do the following:
1. Install R364 to provide a path to GND.
2. Do not use R361, R362, and R363 wit the ADC_VCM output.
3. Make sure DRVDD and AVDD are 3.3V.
4. Do not need to route ADC_CLKOUTM_F…
Hello Jim,
Apologies for the late reply. I have been traveling and have now just starting to catch up to all the E2E questions.
The revision C of the schematic is attached. The major change on this revision is that we have replaced U15 from a 16-bit…
