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Showing 5 results View by: Thread Post Sort by
  • TSW14J57EVM: TSW14J56EVM, TSW14J57EVM, TSW1400EVM : Dual (Quad) 200-500 Msps 10-14 bits ADC+FPGA+ Quad DAC Design Choice for Medical Imaging

    Yamuna Phal
    Yamuna Phal
    TI Thinks Resolved
    Part Number: TSW14J57EVM Other Parts Discussed in Thread: ADS4229 , ADS5517 , TIDA-00826 , TIDA-010128 , Hi - I saw some previous threads on high-speed ADC design applications and I was wondering if someone could help me in picking out the right FPGA-based…
    • over 5 years ago
    • Data converters
    • Data converters forum
  • Answered
  • RE: ADS5517EVM: Spartan XC3S250E default FPGA code availability

    LFRanalog
    LFRanalog
    Resolved
    Hi Richard, Could you please provide me with the FPGA programming file for the ADS5517 EVM (Spartan-3E FPGA) that you mentioned in your original reply? The evaluation module is working fine, but I am unable to revert it to its stock configuration currently…
    • over 7 years ago
    • Data converters
    • Data converters forum
  • Answered
  • Compatibility of ADS5463EVM with DE2-115

    Jose Jauregui
    Jose Jauregui
    Resolved
    Other Parts Discussed in Thread: ADS5463EVM , ADS58B19 , ADS5517 , ADS5474 , HSMC-ADC-BRIDGE Hi, I'm planning to use a DE2-115 to work with the ADS5463EVM, I have asked to Terasic about the speed of the HSMC and the say it can work at 640 MHz and that it…
    • Resolved
    • over 12 years ago
    • Data converters
    • Data converters forum
  • Answered
  • Re: Altera DE2-115 board compatibility with TI's high speed ADC EVMs

    Richard Prentice
    Richard Prentice
    Resolved
    Hi, In general, that list of ADC EVMs is meant to be the list of EVMs that are suitable for use with the HSMC-ADC-bridge into the Altera development platform. There is just one family of EVM on that list that I think we need to be careful of, and it is…
    • over 13 years ago
    • Data converters
    • Data converters forum
  • Answered
  • Re: Problems about ADS58C48

    weibao qiu
    weibao qiu
    Resolved
    Dear Richard, Thanks for you instruction, the problem is solved. As you said, it's a problem in the FPGA since the rising edge and falling edge of clock is not synchronized. And also the data should be buffered at least for one clock otherwise…
    • over 13 years ago
    • Data converters
    • Data converters forum

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