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Showing 7 results View by: Thread Post Sort by
  • ADS5546: Theta JC top specification.

    Joselito Go
    Joselito Go
    TI Thinks Resolved
    Part Number: ADS5546 Other Parts Discussed in Thread: ADS5560 , Tool/software: Hi Experts, I understand that the Theta JC specification mentioned in the datasheet is referring to the bottom. May I have the Theta JC top specification? Keep safe.…
    • over 1 year ago
    • Data converters
    • Data converters forum
  • ADS5546: output code

    Kailyn Chen
    Kailyn Chen
    Part Number: ADS5546 Hello, The datasheet didn't describe the relationship about the input voltage VS output code. For example, if the input voltage is 0.75V , what is the output code? Below is the configuration: Best regards kailyn
    • over 1 year ago
    • Data converters
    • Data converters forum
  • Answered
  • RE: ADS5517EVM: Spartan XC3S250E default FPGA code availability

    Richard Prentice
    Richard Prentice
    Resolved
    Hi, There was a screenshot in the test document that did not come through in copying and pasting into the posting. I am attaching the document itself. Also, back then we had a batch file that we would run that would handle the Xilinx JTAG programming…
    • over 8 years ago
    • Data converters
    • Data converters forum
  • RE: ADS5562EVM: Low SFDR continued: unable to reproduce >80 SNR measurement using the same apparatus

    jim s
    jim s
    ALB, Is your EVM a Rev C board? If so I have attached the schematic. Please make sure all jumpers are set per the board photo I am sending. Take a scope probe (diff probe would be better) and monitor the ADC input across R21 and R26. You should see…
    • over 5 years ago
    • Data converters
    • Data converters forum
  • RE: ADS5560: how to use the parallel CMOS output mode and single-end clock input

    jim s
    jim s
    Jin, The schematic looks good for the most part. Please do the following: 1. Install R364 to provide a path to GND. 2. Do not use R361, R362, and R363 wit the ADC_VCM output. 3. Make sure DRVDD and AVDD are 3.3V. 4. Do not need to route ADC_CLKOUTM_F…
    • over 7 years ago
    • Data converters
    • Data converters forum
  • Answered
  • RE: ADS5560EVM Schematic not accurate in datasheet

    Kang Hsia
    Kang Hsia
    Resolved
    Hello Jim, Apologies for the late reply. I have been traveling and have now just starting to catch up to all the E2E questions. The revision C of the schematic is attached. The major change on this revision is that we have replaced U15 from a 16-bit…
    • ADS61X9-556XEVM-SCH_C.pdf
    • over 11 years ago
    • Data converters
    • Data converters forum
  • RE: OPA2625: How to improve SNR, HD2 and HD3 of an 18-bit SAR ADC when OPA2625 is being used to drive the differential inputs of ADC?

    Michael Steffes
    Michael Steffes
    Couple of quick things Akash, 1. Where is your DC bias current path for the V+ inputs to the op amps? 2. This differential I/O op amp circuit sometimes has a common mode oscillation - probably not here, but we did see that in the OPA838 decomp device…
    • over 2 years ago
    • Amplifiers
    • Amplifiers forum

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