Part Number: ADS5560 Hi TI Team:
The customer has some problems when using ads5560, please help
Application scenario:
1. Differential input V + - v-input range [- 1.78-1.78];
2. Currently, the maximum input core signal frequency is 1MHz
3. External input…
Part Number: ADS5560 Other Parts Discussed in Thread: ADC3660 How do we read back the internal registers in ADC? SPI or parallel method is only supporting write operation. Please clarify
Part Number: ADS5560
Our KMM customers encounter the following questions during the use of ads5560. Please help to answer them
1、 Whether the clock can adopt the differential clock output by FPGA, or still have to use a special clock chip to form a fully…
Part Number: ADS5560 Hello,
I'm using the ADS5560 ADC connected to a FPGA with the following settings:
Mode: LVDS
Sample Frequency: 10MHz
Sample Mode: Low Speed (<=25MHz)
When sampling a 32768 Hz, 300mVpp sine wave, occurs a spike on the transition…
Part Number: ADS5560 At present, Xilinx's FPGA is used in the ads5560 acquisition scheme, and there is a problem of the distortion of the collected sine wave data.
When the ads5560 is configured as a test mode, the data and the data mode mentioned…
Hi Joselito,
Unfortunately, we do not have this data. We have the spec for the ADS5560/62 with this same package, but the sampling rates are vastly different which will affect the spec value. So, it probably isn't the best reference. If it helps, Theta…
Part Number: ADS5560 During the use of ads5560, it is found that the collected data value is incorrect and the duty cycle of the output CLK is also incorrect. The specific conditions are as follows:
1.Mode pin not connect , DFS pin voltage is 3 / 8 drvdd…
Part Number: ADS5560 Team,
Can you share a SPICE model for the ADS5560 or something to show the input structure?
Also, for "Fig. 45 Input Stage", how does this work? Is it discharging the caps after the conversion? Does it discharge the cap and then you…
