Part Number: ADS6129 Hello,
My customer has a question about ADS6129.
[Q]
Please tell me the meaning that the maximum value of reset pulse width is 1us.
Is it not reset normally when I exceed this value?
Best Regards,
Hiroshi Katsunaga
Other Parts Discussed in Thread: ADS6129 Hello,
My customer has a question about ADS6129.
[Q]
Please tell me the register default value for ADS6129.
I read the following post.
However, it is not closed for the answer.
e2e.ti.com/.../1689167…
Other Parts Discussed in Thread: ADS6129 I am using ADS6129 ADC for my current project interfaced with Arria V FPGA. ADC would be configured in LVDS mode with a sampling rate of 250 Msps.
The clock input for the ADC is derived from the Arria V PLL FPGA…
Other Parts Discussed in Thread: ADS6129 Hello,
We are working on ADS6129 design, for configuration of ADC both parallel and serial config modes have been used.
As per the description and timing diagram, serial configuration looks very similar to…
Other Parts Discussed in Thread: ADS6129 I have the ADS6129 coupled to TSW1200 evaluation board. I need to synchronize the ADC acquisition to an external trigger via the FPGA and send the data using a USB 2 or 3 (I already have the small USB card). I…
Other Parts Discussed in Thread: ADS6129 , ADS5463 Hi everybody! Congratulations for the great community out there, I have just subscribed to this board.
I just bought an ADS6129 ADC and a TSW1200EVM to interface with it, and I'm trying to implement…
Other Parts Discussed in Thread: ADS4129 , ADS61B49 , ADS5403 , ADS6129 , ADS5474 Hello
TI is the manufacturer of such ADCs as ADS6129, ADS61B49, ADS4129, ADS5403. The data sheets on these devices don't specify the appearance of error codes due to metastability…
Hi,
Physically, you could supply the clock to the ADC from an FPGA but I do not think you would want to. The ADS6129 is capable of a signal to noise ratio (SNR) of over 70 dBFS, depending on the frequency of the analog input. To preserve this level…
Hi,
The customer is correct on this point, the test pattern modes are useful for verifying the digital connection from the ADC to the FPGA or ASIC that is receiving the data - letting the FPGA designer check that they have their design correct for…
ALB,
Is your EVM a Rev C board? If so I have attached the schematic. Please make sure all jumpers are set per the board photo I am sending. Take a scope probe (diff probe would be better) and monitor the ADC input across R21 and R26. You should see…
