Part Number: ADS6149 Other Parts Discussed in Thread: ADS4149
I'm looking for a low power and low cost 14 to 16 bit ADC that uses the (parallel) LVDS interface. I found the ADS6149. I previously have bought Analog devices and am considering the AD9642…
Part Number: ADS6149 I'm currently working on the design of a circuit using the ADS6149 and I would like to know how to connect the Reset pin. I will use the Serial Interface Configuration.
But I am confused about how the registers are reset .. in the…
Other Parts Discussed in Thread: ADS6149 Hello,
I would like to understand how ADS6149 runs.
I program the registers as below:
register 0x00h = 0x00h
register 0x20h = 0x00h
register 0x3Fh = 0x60h
register 0x41h = 0x40h
register 0x44h = 0x00h…
Other Parts Discussed in Thread: ADS6149 Having developed a working data acquisition board based on the ADS6149 chip, I'm trying to completely characterize its performance using both dynamic (FFT->SFDR/SNR) and static (histogram->INL/DNL) tests. So far…
Part Number: ADS4149 Other Parts Discussed in Thread: ADS6149 , Hello team,
Customer is planning to update ADS6149 to ADS4149, we have questions per below:
Besides power saving, what other advantage does ADS4149 provide?
What is the min ENOB with…
Hi,
The EVM user's guide is the best place to configure the EVM and the device to get the configuration files to start the ADC setup. Please visit the following site for more detail documents:
https://www.ti.com/product/ADS6149?keyMatch=ADS6149%20EVM#tech…
Hi Jim,
Input pulses are applied differentially. For common mode supply we tried both: internal reference from VCM pin and external reference voltage.
The VCM output was 952 mV and external reference 955mV and pretty much the same voltage was observed…
Hi,
I did round up an EVM for this device and try it on the TSW1405. I found that the LVDS DDR clock signal *is* inverted compared to the ADS6149 EVM, either in the trace routing in the EVM or in the data sheet definition for the DDR data format. I…
Eli,
when you say non-related to a specific design, I am guessing that our source code for the LVDS parallel bus format would be best suited. The source code defines inputs to the FPGA for all the possible LVDS pairs that are listed in the schematics…
