although we have curve about input impedance vs frequency in our d/s, but customer still ask accurate input impedance at 172.8MHz,so pls help on it.
thanks
Hi,
Please see the answer under the questions,
We have a ADS62P43 and are attempting to interface it with a Xilinx FPGA development board over a 136-pin Samtec connector. Can we drive the ADC clock (CLKP/CLKM) using a differential clock output from…
Other Parts Discussed in Thread: ADS62P43 , SN74AVC16244 Hi,
I am working with a ADS62P43 EVM board. I had purchased this board , but it was found defective . After several troubleshooting steps , I couldnt get a clock output from the board. SO I was…
Part Number: ADS42JB69 Other Parts Discussed in Thread: LMH6554 , ADC3664 , ADS62P44 , ADS62P43 , ADC16DV160 Hello,
We purchased a DC-coupled, single-ended ADC card with a ADS42JB69 ADC that is being driven by a LMH6554. The ADC driver circuit follows…
Wally,
Are you experiencing an incompatibility other than the name 'ADS62P23' is not available in HSDC Pro?
Will you please try selecting 'ADS62P43' in HSDC Pro and try to capture data? The scale should be off because the software expects a 14-bit…
Mahadevan,
The first thing we should check is the output data format setting on ADC sided based on the FPGA input data format setting.
The ADS62P43 output data including clock output has two formats for both CMOS and DDR LVDS output modes, one is…
Other Parts Discussed in Thread: ADS62P43 , TINA-TI , THS5671A , ADS62P42 Hello.
Could any one help me how to get spice model not for simulation only design layout library for ADS62P43.
Dose ti supply spice model's?
Other Parts Discussed in Thread: ADS62P48 Hi! Briefly, my question is, when the ADC's reset pin is connected to a controlling pin of another chip ( NOT hare wired to ground, and this controlling chip and the ADC are powered up at the same time. So the…
