Hello Matt,
No in fact I was not waiting 50ms. Thanks for the tip. However, since fixing this, I am getting all zeros from the registers after powerup. Only the 0xB bit 27 is high. This is, BTW, with the ads62p48 evm.
My spi interface is implemented…
Other Parts Discussed in Thread: CDCE72010 , ADS62P48 I need the REV D of ADS62PXXEVM I already find the REV A and REV B I have(SLAU237b[1].pdf and SLAU237A[1].pdf)
Thanks
I've been getting this in one of your newsletter for the past few months... Needs correction: Dual-Channel, 14-Bit, 210-MSPS ADC with DDR LVDS and Parallel CMOS Outputs: At 210 MSPS , the ADS62P48 high-performance ADC is 600 MSPS faster than the…
Other Parts Discussed in Thread: ADS62P28 Hi,
I have a QAM demodulator consisting of ADS62P28 connected to Spartan-6 FPGA using parallel CMOS signals (FPGA latches data using CLKOUT from ADC).
When sampling incoming signal at 140 MSPS (or lower rates…