Part Number: ADS62P49
The datasheet page 10 says that: All digital inputs support 1.8V and 3.3V CMOS logic levels.
Can I use LVCMOS 2.5 logic? I would like to eliminate the use of a superfluous level translator.
Part Number: ADS62P49 We are reviewing "ADS62P49EVM". I'm asking because I think there is something wrong in the circuit schematic.
ADC's Clock Out Pin seems to have the wrong polarity. Please check.
Thank you.
Part Number: ADS62P49 We have designed and tested a board using the ADS62P49. We are digitizing data at 200 MHz, and initial testing showed reasonable results. While integrating this board with our system, we had some issues that caused us to look more…
Part Number: ADS62P49 I am seeing a fixed DC offset in the output of adc when it is set in LVCMOS mode vs when it is set in LVDS output mode. When I give input as sine wave of 10dBm 1MHz frequency, the output of LVCMOS mode is centered at 0 . However…
Part Number: ADS62P49 Hi I am working on a FMC150 card which has ADS62P49 ADC for analog to digital conversion. However, FMC150 datasheet has mentioned the FMC pin layout only in terms of 7 pairs of LVDS _P and _N outputs.
I want to use ADC in LVCMOS…
Part Number: ADS62P49 Hi I am using FMC150 card having ADS62p49 on a Xilinx ZC706 board LPC connector. I have provided 10 MHz input and when i see the samples coming out of ADC on ILA of Xilinx, the digital output is sine wave but the amplitude of sine…
Part Number: ADS62P49 Other Parts Discussed in Thread: CDCE62005 HI,
I am using DAC34SH84EVM to provide CLK 250 MHz for the TSW4200-ADC (ADSP62P49).
I am using an Ext CLK 1 GHz at J9 and I got output CLK of 250 MHz at J10 J11. The divided output CLK then…
Part Number: ADS62P49 I am testing the data collection with ADS62P49. When the register is configured according to the register table, it is found that when the input end of AD is suspended, the output collection data of AD is only 0X3FFF and 0x0000.I…
Part Number: ADS62P49 I am testing the data collection with ADS62P49. When the register is configured according to the register table, it is found that when the input end of AD is suspended, the output collection data of AD is only 0X3FFF and 0x0000.I…