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  RajK

  • 1 month ago
  • Data converters
  • Data converters forum

  RE: ADS54J66: JESD loses sync intermittently

  Thank you for the link, Jim. I have started the replacement process. I have a question regarding the operation of ADS54J66 when sync has been established. Is the link supposed to remain stable and in sync as long as the power supply and clock are stable...
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  Pankaj Kataria

  • over 2 years ago
  • Data converters
  • Data converters forum

  ADS6442: Precision of resistors/caps on the analog inputs of the ADC

  TI Thinks Resolved

  Part Number: ADS6442 Hello, I do not see the analog input impedance spread specified in the datasheet. I presume that it is on the order of +-10% If that is the case then I don't need to put high precision input resistors and capacitors along...
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  Pankaj Kataria

  • over 2 years ago
  • Data converters
  • Data converters forum

  ADS6442: Test Pattern Out with considerable delay

  Part Number: ADS6442 Hello, After programming the ADC (P/N ADS6442_RGC_64) to pump out specific desired test pattern, I have to wait for 7 rising edges of FRAME signal before the test pattern is fully read out. This surprised me as I thought that...
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  Pankaj Kataria

  • over 3 years ago
  • Data converters
  • Data converters forum

  ADS6442: What range of capacitances can be added to pin # 5 (CAP)?

  Part Number: ADS6442 I have designed in TI’s ADC ADS6442_RGC_64 in our prototypes currently being manufactured. Per TI’s specification I am using a 2nF capacitor on pin 5 (CAP). I picked a 2nF/50Vdc, 10%, 0402, X7R. The layout is already...
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  Richard Prentice

  • over 4 years ago
  • Data converters
  • Data converters forum

  RE: ADS6442 fully diff op-amp

  Hi, Yes, as described on page 48 of the datasheet: The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically...
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  Ray DuVarney

  • over 4 years ago
  • Data converters
  • Data converters forum

  Compatibility of ADS6442 with ADS52J90 ADC

  Question: We would like to use the ADS6442 in parallel with the ADS52J90 to make a total of 20 inputs with the ADS52J90 in 16 input mode. I know the inputs are compatible but are the serial outputs? The big issue is latency. Would the framed serial...
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  ashok m

  • over 8 years ago
  • Data converters
  • Data converters forum

  Deserializer for ADS6442 virtex6

  • Resolved

  we want to evaluate ADS6442 by interfacing with ML605 (virtex 6) FPGA using ADS6442EVM and FMC ADC
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  Garry Motter

  • over 9 years ago
  • Data converters
  • Data converters forum

  DC coupling a single ended signal on ADS644x

  • Resolved

  This is a somewhat unconventional application. We have a sensor that puts out an analog signal that ranges from 0.8v to 2.8v. We need to digitize the actual voltage, so we can't AC couple with capacitors or transformers. Using the differential input "as intended" doesn't really seem...
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  LeonardEllis

  • over 7 years ago
  • Data converters
  • Data converters forum

  ADS8548 VQFN(RGC) Footprint Files

  • Resolved

  Footprint files for the VQFN package are not on the webpage. I found VQFN for the ADS6442
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  Andrey5924

  • over 7 years ago
  • Clock & timing
  • Clock & timing forum

  RE: 32MHz out of 10MHz reference

  Hello Timothy, Thank you for your reply. I will certainly check the parts you recommended. To answer your questions, required Clock Format is LVCMOS. Jitter of 10 MHz clock 1ps rms in bandwidth 12 kHz to 20 MHz. We would like to keep the ultra low...

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