Part Number: ADS7279 We are observing the MISO data changing on the falling edge of SCLK
We can flip the interface to use the rising edge if this is the correct solution, but this is not what the datasheet describes. Please advise.
Other Parts Discussed in Thread: ADS7280 I have an application where I would like to control the ADS7280 with just a simple 4-wire SPI interface (SCLK,SDI,SDO,CS). In other words, I would like to initiate acquisition and conversion sequences through the…
The same question is valid also for chips like ADS8471 and ADS7279. The latter for instance, has SFDR specified only up to 100 kHz, but has a 30 MHz BW.
Tom,
My customer has changed their requirements on this design, and I need your help to narrow down the right part.
Here are some recent conversations with him:
