Part Number: AFE5801AFE5801 have no LVDS signal output,
My design is as follows:
1、The difference clock is generated by FPGA PLL，ac couple to CLKP pin and CLKM ping .Vpp is 3.3V（and later attempt reduced voltage to 1.8v, but to no avail）
When I…
Part Number: AFE5801 Hi,
I want to capture data from AFE5801 EVM with TSW1400 EVM. However, the AFE5801 GUI I found does not include the option that init for TSW1400, only has init for TSW 1250, which is not likely the same version from the user guide…
Hi,
Thanks for using AFE5801 device.
for your question:
This is noise density for 100dB.
After integrating BW, then we get 70dBFS SNR.
Thank you!
Best regards,
Chen
Hi praveen,
Thank you for the quick reply
As mentioned in the e2e.ti.com/.../1847967 post, even if I receive a bridge adapter card with the kit. Can that adapter card be used with TSW1405? as the bridge adapter which i receive in the kit is for TSW1400…
Part Number: AFE5801 Hi team,
The customer has two questions for AFE5801.
Q1: Can the customer use AFE5801 as an ADC, the output signal of AFE5801 is connected to FPGA?
Q2: Can the clock(CLKP/N pins) of AFE5801 be provided by PLL of FPGA? Or need…
Part Number: AFE5801 Hello,
The AFE5801 has written about length matching of digital output signals which is 150 mils.
but there is no statement regarding length matching of Analog inputs so, please let us know that "is there any length matching requirements…
Part Number: AFE5801
Hi team,
The customer is using AFE5801. When he does not connect the external crystal, there is a common voltage in CLKP pin and CLKM pin
The two voltages are the same . It is 0.975V. The supply voltage 3.3V and 1.8V are fine…
Part Number: AFE5801 Hi team,
The customer is using AFE5801. On page 9 of the datasheet, the customer needs to verify the output sequence of the output signal.
Does the signal output from D11 to D0 or from D0 to D11? Or other output sequence?
Best…
Part Number: AFE5801 Hello,
I am trying to write the vhdl code to get the output data from the afe5801 using FPGA.
I am having trouble understanding how clocks work and digital output form（MSB? or LSB first?）, any reference Verilog HDL or VHDL code…
