Part Number: AFE5832 Hi Experts,
We'd like to ask about implementation of AFE5832:
Over the past several months, we have configured our device, that includes AFE5832, to a desireable state. However, I just found out that LNA_HPF_PROG is set to "11…
Part Number: AFE5832 Tool/software: Hi,
We are currently using the AFE5832 chip for the design of ultrasonic non-destructive testing equipment. Our development platform is based on the Zynq-7000 series.
To assist our development process, we would…
Part Number: AFE5832 Tool/software: Dear TI Support Team,
I am evaluating the AFE5832 for an ultrasound receive chain and have a question about its behavior in TGC (Time‑Gain Control) mode.
When the device steps the gain in TGC mode, is any momentary…
Part Number: AFE5832 Tool/software: Does the odd VCA register have no way to read and write anymore if we used AFE5832 in the pcb and PIN K15 is NC? Thanks.
Part Number: AFE5832LP Other Parts Discussed in Thread: AFE5832 Hi Sir/Madam,
Could you please tell me what should I do to avoid phase influences of TX_TRIG on sampling (I connect TX_TRIG signal to line_start) after I finished configuration of PLL …
Part Number: AFE5832 Other Parts Discussed in Thread: AFE58JD32 Tool/software: The Pin K16 in the datasheet of afe5832 is NC, but the reference design is SPI_DIG_EN. This question bothers me. Can you give me some advice? Thanks.
Part Number: AFE5832 Tool/software: Hi, My friend.
I would like to know. Is the "2ns" here intended to represent the holding time?
Why is it the delay between the falling edge of TCG and the rising edge of clk, rather than the delay between the rising…
Part Number: AFE5832LP Other Parts Discussed in Thread: AFE5832 Hi Sir/Madam,
I configured LPF registers of analog end of AFE5832, but it seemed not working. My questions are: 1.do I need to configure PLL clock then I can configure LPF registers---I…
Part Number: AFE5832 Tool/software: Hi Sir/Madam,
Could you please give me some suggestions or helps regarding configuration of the AFE 5832's LNA-HPF and LPF. The beamformed signal and then b-mode imaging seems having no changes after I configured…
Part Number: AFE5832 Dear Sir/Madam,
During my serdes of ramp mode test pattern data sent from the afe 5832 on FPGA side, I found there is a fixed delays of 25-29 clks (my sampling frequence is 32MHz) between the 1st 8 channels and the last 8 channels…
