Part Number: AFE5832LP
Tool/software:
Hello,
While researching ultrasound beamforming solutions, I came across the application report "sboa361.pdf," which references a Transceiver Board. However, I couldn’t locate any detailed information or resources about this board.
Is this board available for purchase, or are there any schematics or PCB files related to it?
Thank you for your help!
Part Number: AFE5832LP
Tool/software:
I am not sure if I understand the AFE_PDN_FAST specifications
1) AFE_PDN_FAST requires 8us to wake up
2) but only if last woken up <500us previously, failing which it requires 4ms to power up.
What method is recommended to keep the device in partial power down (and not fully powered down)?
If a (-ve) pulse is sent every 500us for 18us? or is a longer pulse required (and for how long)?
Our current operational sequence is as follows, but the automatic DC Offset indicates that the capacitors are still charging up after 18us (8+8+2us).
1) -ve pulse the AFE_PDN_FAST (wake up)
2) wait 8us for wake up
3) TX_Trig (to synchronise AFE)
4) power up the TX (using TX7332)
5) wait another 8us (for TX7332 to wake up)
6) pulse the TX7332
7) wait 2us for TX7332 to pulse and TR switch to activate
8) shut off power to TX7332.
8) start capturing on the AFE
9) end capturing
10) send AFE_PDN_FAST (+ve) to put AFE back into power down.
process the data and send to imaging.... and repeat.
Our processing takes <200us, so meeting the 500us requirement, yet the automatic DC-offset is not yet settled (in the 16us between AFE_PDN_FAST=0 to start capturing).
Please advise.
Part Number: AFE5832LP
Tool/software:
Hi,
Please tell me about the digital HPF settings.
When the digital HPF is enabled, to select the HPF, can I write the just k value itself to the register?
Or, for example, is the assignment as follows?
Setting 0 to the register selects k=2
Setting 1 to the register selects k=3
:
Regards,
Part Number: AFE5832LP
Tool/software:
Hi,
Please tell me about the initialization of the AFE5832LP.
(1) What kind of malfunctions are expected to occur if the contents of section 10.4 of the datasheet are not performed?
(2) Are the following three registers the only ones related to "1. Write all bits marked 1 in all the register maps"?
・address 0x3 bit[4]
・address 0xD1 bit[2:0]
・address 0xD4 bit[0]
Regards,
Part Number: AFE5832LP
Dear engineers,
We have got Swaroop board and installed the HSDC Pro and AFE5832LPTX EVM,and realized the data collection.
Now we looking forward to design a Ultrasonic imaging system.
We plan to make some changes on existing Swaroop board,
Could you provide an SDK file for the HSDC Pro?
In addition to that,We tried to compile the project files of the FPGA on our computers.And we failed.
The project files of FPGA are from the software of 'SwroopFPGA-7.0-windows-installer.exe'installation path.
Could you explain why and provide a solution?
Finally, we hope to get more details about Swaroop board, for example data transfer speed and amount of data storage.
We look forward to hearing back from you soon.
Best regards,
Xingzhao Liu
Part Number: AFE5832LP
Dear TI Teams,
When using the AFE5832LP in one of our projects, we encountered some problems with LVDS data reception, the details are as follows:
We know that the default of AFE5832LP is to transmit data of two AD acquisition channels on one LVDS line, and a total of 16 LVDS lines are used to transmit 32 channel datas, and the high FCLK is fixed to correspond to the even number of channels, and the low FCLK corresponds to the odd number of channels. At present, due to the limitation of system IO, we are using one LVDS line to transmit data from 4 AD acquisition channels, and a total of 8 lines are used to complete the acquisition and transmission (LVDS RATE 2X mode). In this case, the 4 channels acquired data at once are transmitted on a single LVDS line., corresponding to an acquisition of FCLK has two high level cycles and two low level cycles, will represented in high, low, high, low form, corresponding to the AD acquisition channel of 1st-ch, 3rd-ch, 2nd-ch, 4th-ch. Therefore, when FCLK is in high level, we can not determine whether the current corresponding to the data of channel 1 or channel 3 data.
From the datasheet we learned that after a certain delay time after TX_TRIG, the FCLK signal will regularly appear in high, low, high, low pulse signals, and then the first high signal corresponds to the data of the first channel. However, we found that the delay time is not fixed after each TX_TRIG generation, which will cause the confusion of solving the data channel. That is, the external input is fixed at 1 channel input, but after solving the data, sometimes the waveforms appear in the frist channel and sometimes in second channels.
May I ask if there is some mechanism to know exactly this correspondence?
Thanks,
Kind Regards
Part Number: AFE5832LP
Tool/software:
I see this question from 1 year ago.
How can I obtain the two cfg files mentioned?
6470.init.cfg and AFE5832_LVDS_12x_12b_CMD.cfg.
thank you.
Part Number: AFE5832LP
Tool/software:
Hello
I am developing wireless ultrasound equipment using the AFE5832LP.
When power is supplied and the AFE5832LP is initialized, the RX function operates normally.
However, when I power on the AFE5832LP only during the scan phase (32 ms) and turn off the power during the wireless transmission phase (100 ms), noise appears in the ultrasound image.
Initially, there is no noise, but after heating, noise appears on the right side of the image. During wireless transmission, only the power to the wireless module is turned on.
The reason for operating in this manner is to reduce heat generation.
When the power is kept on continuously, this issue does not occur.
Additionally, since no problem is observed when applying a ramp pattern, it seems unlikely that the issue lies beyond the ADC stage.
I would like to ask about the possible cause of this noise under these conditions.
Thanks.
Part Number: AFE5832LP
HI,
I'm writing vhdl code to set up the AFE5832LP at start up, to generate a pattern.
I have followed the start up sequence as described in the datasheet but is not working, I have no signals coming from the devices.
I have attached the vhdl code for the setting up.
Part Number: AFE5832LP
HI Dear,
Could you please provide full datasheet of part#AFE5832LPZAV?
Thanks.
Eva