Part Number: AFE58JD32 Tool/software: Hello E2E forum,
I am seeing inconsistencies when configuring the AFE58JD32 for the LVDS ramp pattern (from the ADC, not the demodulator). Sometimes the zero value following a TX_TRIG appears on the data word corresponding…
Hi,
Datasheet plots are taken with some specific load . TX7364 datasheet load is 400Ω||125pF and your load is 300Ω||200pF. The hd2 performance wont change across these loads .
For AFE58JD32 input resistance assumed is 50Ohm in datasheet and this…
Part Number: AFE58JD32 Tool/software: Hello,I hope this message finds you well.
I am currently using an FPGA to drive the AFE58JD32, and I plan to connect them via the LVDS interface. During the design process, I would like to confirm whether there is…
Part Number: AFE58JD32 Other Parts Discussed in Thread: AFE58JD18 , Tool/software: Hello,
I'd like to ask what is the maximal sampling frequency at 12 bits resolution for 2-lane JESD configuration?
Best regards,
Mateusz Walczak
Part Number: AFE58JD32 I am using the LVDS mode of AFE58JD32 for data acquisition. I can collect the correct ramp data, sync data and deskew data. There is a problem when collecting ADC data.
Now I have two questions:
1.When I collect ADC data after…
Part Number: AFE58JD32 Other Parts Discussed in Thread: AFE58JD28 Dear Expert
Last time I post E2E https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1192682/afe58jd32-difficulty-synchronizing-8-pieces-of-afe/4497301…
Part Number: AFE58JD32 Other Parts Discussed in Thread: AFE58JD28 , Dear Sir
Difficulty synchronizing 8 pieces of AFE
For our portable color Doppler ultrasound project, 8 pieces of AFE cannot be synchronized according to the following initial configuration…
Part Number: AFE58JD32 For simulating the JESD204B high-speed transmission link between AFE58JD32 and KINTEX7 XC7K325T_FFG900, with 2 inches of total PCB trace, I request for AFE58JD32 IBIS-AMI Model.
Please.
Thank you!
Part Number: AFE58JD32 During AFE58JD32 schematic design, we have shorted 4 TR_EN pins ( TR_EN[1], TR_EN[2], TR_EN[3], TR_EN[1] ) of a AFE and made to single connection and is given to our FPGA due to non availability of pins.
When gone through datasheet…