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  • AFE58JD32LP: Register 4 not writing

    Part Number: AFE58JD32LP Tool/software: Hi Team, I'm having an odd issue with the AFE58JD32LPZAV. We have 2 designs the first a basic prototype focused on feasability and the second being the final product. The first design worked perfectly, however…
    • Answered

  • AFE58JD32LP: back-to-back Schottky clamping diodes

    Resolved
    Part Number: AFE58JD32LP Tool/software: I am currently designing an ultrasound system using the AFE58JD32LP. In the datasheet, specifically section 9.3.1.6, TI recommends using back-to-back Schottky clamping diodes at the input to limit large overload…
    • Resolved

  • AFE58JD32LP: Can SEN pin be constantly tied Low?

    TI Thinks Resolved
    Part Number: AFE58JD32LP Hello dear community. I am going to use the AFE58JD32LP and (since the design is almost finished) in short of SPI connections The AFE has it's own designated SPI bus (1:1 with the FPGA), so I thought that I don't need to use the…

  • AFE58JD32LP: DCLK output clock offset

    Part Number: AFE58JD32LP Other Parts Discussed in Thread: AFE58JD32 Hi, team: My customer use AFE58JD3LP in their ultrasound, The DCLK of AFE58JD32 is output by AFE 480MHz, but the measured clock offset is very large, more than 6%. Minimum :448MHz, maximum…

  • AFE58JD32LP: Power Usage

    TI Thinks Resolved
    Part Number: AFE58JD32LP Hi, Good day. Our customer have a question regarding the AFE58JD32LP. Kindly see below. The datasheet gives the current draw per net. It also giver the power dissipation per channel. I am wondering if the current draw per nets…

  • RE: AFE5808AEVM: PCB Board layout

    Hi, For demod feature usage we would recommend to separate the grounds. AFE58JD32LP has this feature whereas AFE5808A does not have this feature . If you are using AFE5808A you can follow AFE5808AEVM scheme .
    • Answered

  • RE: AFE5832LP: initialization

    Resolved
    Without initialization it may work but not recommended by TI. Reg 0x90H bit 10 is marked 1 in datasheet - You can ignore this . This is for AFE58JD32LP.

  • RE: AFE58JD32: Max sampling frequency for JESD 2 lane config

    Yes correct . Each channel sampling will be half of clock frequency . Same will be applicable for AFE58JD32LP device.
    • Answered

  • RE: AFE5832LP: The issue of inconsistent pins between the evaluation board and datasheet

    Resolved
    Hi, EVM is built to support AFE5832LP and AFE58JD32LP . So the difference in AFE5832LP datasheet and evm is because of that . These additional pins does not affect the functionality/performance of the AFE5832LP chip. You can follow the datasheet guidelines…

  • RE: AFE58JD32LPEVM: GUI download.

    Hello Ryu, Thanks for reaching out and for your interest in AFE58JD32LP. AFE58JD32LP collaterals are shared under NDA. Please ask your client to request for the AFE58JD32LP collaterals and other design resources by clicking on the ‘Request Now’ button…

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