Part Number: AFE58JD48 hello,
I am using FPGA to configure AFE58JD48. I want to verify the JESD204B link. However, after configuring some registers, I found that the JESD204B IP CORE in the FPGA did not show any received data. Please help to confirm…
Part Number: AFE58JD48 We have a few questions about your AFE5848s. We recently found a single channel on one AFE with a higher DC offset than we would expect – when all of the other channels had an offset within +/-500 counts, this one’s offset was at…
Part Number: AFE58JD48 Hi Sir,
the PDN_CH register can be used to power down VCA of each channel
on datasheet, bit 0 maps to CH1, bit 1 maps to CH2... bit 15 maps to CH16
However, in our test, it looks like the order should be reversed, ie. bit 0 maps…
Part Number: AFE58JD48 Hi Sir,
below is the diagram of CW mode circuit of one AFE58JD48 chip, each AFE58JD48 chip has 16 channels, the CW mode signal of the 16 channels are summed by the summing amplifier at the right hand side of the figure
there…
Hi
Thanks for your confirmation. Let me know if need any further help. If it solves the issue then please close this thread by clicsing on "Issue resolved" button.
Regards,
Shabbir
Part Number: AFE58JD48 Other Parts Discussed in Thread: LMK00301 , LMK04832 hello:
I am planning to synchronize multiple AFEs with JESD204B. Currently, I encountered some issues in PCB design as shown in the picture. I am using LMK04832 to output DEVICE…