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  • RE: AFE58JD48EVM: Query Regarding Multi ADC synchronization for AFE58JD48EVM

    This looks fine . Here are few recommendations 1) Length match clk and sysref signals 2) Length match clk across device 3) Are you using TX_TRIG ? This is required to align the data across device if you are using demod / test pattern . This also needs…

  • RE: AFE58JD48EVM: AFE58JD48EVM: Insertion loss of the SerDes traces from ADC digital output to FMC Connector

    Hi Lalit , If I understand correctly you want to use AFE58JD48EVM with your FPGA card for evaluation . What is the limitation of using TSW14J50 capture card ? Below is the routing guidelines . https://www.ti.com/lit/ml/slap162/slap162.pdfin We are using…

  • AFE58JD48EVM: Query regarding the Equalization capabilites of AFE58JDEVM

    Part Number: AFE58JD48EVM Other Parts Discussed in Thread: AFE58JD48 , Tool/software: Hi, We are working with AFE58JD48EVM, we want to test 160X mode at 78.125MSPS samling rate, which corresponds to 12.5Gbps lane rate. We are oprating at 312.5 MHz device…

  • AFE58JD48EVM: clock tree : purpose of the CDCM1802 component

    TI Thinks Resolved
    Part Number: AFE58JD48EVM Other Parts Discussed in Thread: CDCM1802 , , LMK04826 Tool/software: Hi, I would like to understand the clock tree of the AFE58JD48EVM : What is the role of the CDCM1802 component? The JESD interface between the FPGA and the…

  • RE: AFE58JD48EVM: Query regading the ADC sample MSB bit

    Duplicate thread e2e.ti.com/.../afe58jd48evm-query-regarding-deterministic-latency-one-device-clock-cycle-variation

  • AFE58JD48EVM: Query regarding deterministic latency one device clock cycle variation

    Part Number: AFE58JD48EVM Other Parts Discussed in Thread: LMK04826 , AFE58JD48 Tool/software: Hi, We are testing determistic latency for AFE58JD48EVM with JESD204B RX IP on EFINIX FPGA, I have attached the setup we are using for your reference. We…

  • RE: AFE58JD48EVM: AFE58JD48EVM

    Feng Tao, As I understand, you only need a single trigger between captures. I replicated your configuration (TSW14J50EVM + AFE58JD48EVM). Try the following: 1. Enable Trigger Mode 2. Connect Waveform Generator Source to J13 "EXT TRIG" 3. S…
    • Answered

  • AFE58JD48EVM: Getting capacitive effect on the square wave ADC input on lower frequency

    Resolved
    Part Number: AFE58JD48EVM Tool/software: Hi I am working with AFE58JD48EVM eval board to send the ADC data over JESD204B interface to FPGA and then plotting the extracted data on the JESD204B RX on wavevision. I am sending a 1MHz 400mVpp square wave at…
    • Resolved

  • AFE58JD48EVM: Capacitors in the LMK to FPGA Sysref Path

    Part Number: AFE58JD48EVM Tool/software: I want to achieve Deterministic Latency using AFE58JD48EVM. I am planning to use Sysref Pulsed in my application (1 Sysref Pulse) I found capacitors in the Sysref Path from LMK to FPGA My Queries are Can single…

  • AFE58JD48EVM: How to Change LMK Clock rate

    Part Number: AFE58JD48EVM Other Parts Discussed in Thread: AFE58JD48 Tool/software: Hi TI Team, I am using AFE58JD48 ADC Chip, I have not found any LMK related configuration tab in the AFE58JD48_EVM GUI so i am not able to change the clock rates. But there…

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